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AgeCommit message (Expand)Author
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt
2016-06-07ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processorsBenjamin Herrenschmidt
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt
2016-06-07target-ppc: fixup bitrot in mmu_helper.c debug statementsMark Cave-Ayland
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt
2016-06-07target-ppc/fpu_helper: Fix efscmp* instructions handlingTalha Imran
2016-06-05target-*: dfilter support for in_asmRichard Henderson
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt
2016-05-30ppc: Get out of emulation on SMT "OR" opsBenjamin Herrenschmidt
2016-05-30ppc: Fix sign extension issue in mtmsr(d) emulationMichael Neuling
2016-05-30ppc: Change 'invalid' bit mask of tlbiel and tlbieBenjamin Herrenschmidt
2016-05-30ppc: tlbie, tlbia and tlbisync are HV onlyBenjamin Herrenschmidt
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt
2016-05-30ppc: Remove MMU_MODEn_SUFFIX definitionsBenjamin Herrenschmidt
2016-05-27spapr_iommu: Finish renaming vfio_accel to need_vfioAlexey Kardashevskiy
2016-05-27PPC/KVM: early validation of vcpu idGreg Kurz
2016-05-27target-ppc: Cleanups to rldinm, rldnm, rldimiRichard Henderson
2016-05-27target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotateRichard Henderson
2016-05-27target-ppc: Use movcond in iselRichard Henderson
2016-05-27target-ppc: Correct KVM synchronization for ppc_hash64_set_external_hpt()David Gibson
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini
2016-05-19hw: move CPU state serialization to migration/cpu.hPaolo Bonzini
2016-05-19ppc: use PowerPCCPU instead of CPUPPCStatePaolo Bonzini
2016-05-19target-ppc: make cpu-qom.h not target specificPaolo Bonzini
2016-05-19target-ppc: do not make PowerPCCPUClass depend on target-specific symbolsPaolo Bonzini
2016-05-19target-ppc: do not use target_ulong in cpu-qom.hPaolo Bonzini
2016-05-19cpu: make cpu-qom.h only include-able from cpu.hPaolo Bonzini
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota
2016-04-18ppc: Fix migration of the XER registerThomas Huth
2016-04-18ppc: Fix the bad exception NIP value and the range check in LSWXThomas Huth
2016-04-18ppc: Fix the range check in the LSWI instructionThomas Huth
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater
2016-03-24Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2016-03-24ppc: move POWER8 Book4 regs in their own routineCédric Le Goater
2016-03-24ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt
2016-03-24ppc: Add dummy CIABR SPRBenjamin Herrenschmidt
2016-03-24ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt
2016-03-24ppc: Fix writing to AMR/UAMORBenjamin Herrenschmidt
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