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2013-03-08target-ppc: Extract 603e aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 740/750 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 750 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7x5 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7400 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7410 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7448 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7450 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x1 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x5 as aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x7[A] aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn "ppc32" and "ppc64" CPUs into aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 440 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 40x aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MGT823/MPC8xx as aliasesAndreas Färber
They used different PVRs but were defined to MPC8xx. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC5xx aliasesAndreas Färber
Their PVR differed but was defined to MPC5xx. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Make -cpu "ppc" an alias to "ppc32"Andreas Färber
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64. If we ever want to change it, we can more easily do so now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract aliases from definitions listAndreas Färber
Move definitions that were 100% identical except for the name into a list of aliases so that we don't register duplicate CPU types. Drop the accompanying comments since they don't really add value. We need to support recursive lookup due to code names referencing a generic name referencing a specific model revision. List aliases separately for -cpu ?. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Inline comma into POWERPC_DEF_SVR() macroAndreas Färber
To repurpose the POWERPC_DEF_SVR() macro outside of an array, move the comma into the macro. No functional change. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Drop nested TARGET_PPC64 guard for POWER7Andreas Färber
It is within a large TARGET_PPC64 section from 970 to 620, so an #endif /* TARGET_PPC64 */ is confusing. Clean this up. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Update error handling in ppc_cpu_realize()Andreas Färber
Commit fe828a4d4b7a5617cda7b24e95e327bfb71d790e added a new fatal error message while QOM realize'ification was in flight. Convert it to return an Error instead of exit()ing. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix "G2leGP3" PVRAndreas Färber
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the "G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR. Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to "G2leGP3". Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix CPU_POWERPC_MPC8547EAndreas Färber
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21. Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show. Fixing this nontheless helps with QOM'ifying CPU aliases. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber
Introduce ENV_OFFSET macros which can be used in non-target-specific code that needs to generate TCG instructions which reference CPUState fields given the cpu_env register that TCG targets set up with a pointer to the CPUArchState struct. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-25target-ppc: Fix SUBFE carryRichard Henderson
While ~T0+T1+CF = T1-T0+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-23target-ppc: Compute mullwo without branchesRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Compute arithmetic shift carry without branchesRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Implement neg in terms of subfRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Use add2 for carry generationRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Compute addition carry with setcondRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Compute addition overflow without branchesRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Use setcond in gen_op_cmpRichard Henderson
Which means that callers need not copy data into local tmps. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Split out SO, OV, CA fields from XERRichard Henderson
In preparation for more efficient setting of these fields. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-ppc: Use mul*2 in mulh* insnsRichard Henderson
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber
The target-specific ENV_GET_CPU() macros have allowed us to navigate from CPUArchState to CPUState. The reverse direction was not supported. Avoid introducing CPU_GET_ENV() macros by initializing an untyped pointer that is initialized in derived instance_init functions. The field may not be called "env" due to it being poisoned. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-ppc: Move TCG initialization to PowerPCCPU initfnAndreas Färber
Ensures that a QOM-created PowerPCCPU is usable. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-ppc: Update PowerPCCPU to QOM realizefnAndreas Färber
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set realized = true in cpu_ppc_init(). Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-11error: Strip trailing '\n' from error string arguments (again)Markus Armbruster
Commit 6daf194d and be62a2eb got rid of a bunch, but they keep coming back. Tracked down with this Coccinelle semantic patch: @r@ expression err, eno, cls, fmt; position p; @@ ( error_report(fmt, ...)@p | error_set(err, cls, fmt, ...)@p | error_set_errno(err, eno, cls, fmt, ...)@p | error_setg(err, fmt, ...)@p | error_setg_errno(err, eno, fmt, ...)@p ) @script:python@ fmt << r.fmt; p << r.p; @@ if "\\n" in str(fmt): print "%s:%s:%s:%s" % (p[0].file, p[0].line, p[0].column, fmt) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-id: 1360354939-10994-4-git-send-email-armbru@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-01cpu: do not use object_deletePaolo Bonzini
CPUs are never added to the composition tree, so delete is achieved simply by removing the last references to them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-01target-ppc: Fix target_ulong vs. hwaddr format mismatchesAndreas Färber
Since HWADDR_PRIx is always the same now, use %016 for TARGET_PPC64 and %08 for common code. This may slightly change the ppc64 debug output. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-01target-ppc: Fix build for PPC_DEBUG_DISASAndreas Färber
In r5949 / 76db3ba44ee8db671f804755f13b016eefd13288 (target-ppc: memory load/store rework) variable little_endian was replaced with ctx.le_mode. Update the debug code. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-02-01target-ppc: Fix unused variable warning for FLUSH_ALL_TLBSAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-02-01PPC: Unify dcbzl code pathAlexander Graf
The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4. Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. While at it, also refactor the code to check the 970 special case during runtime. This way we don't need to differenciate between a 970 dcbz and any other dcbz anymore. We also allow for future improvements to add e500mc dcbz handling. Reported-by: Amadeusz Sławiński <amade@asmblr.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-01-27cpu: Add model resolution support to CPUClassAndreas Färber
Introduce CPUClass::class_by_name and add a default implementation. Hook up the alpha and ppc implementations. Introduce a wrapper function cpu_class_by_name(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27kvm: Create kvm_arch_vcpu_id() functionEduardo Habkost
This will allow each architecture to define how the VCPU ID is set on the KVM_CREATE_VCPU ioctl call. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-25target-ppc: Give a meaningful error if too many threads are specifiedMike Qiu
Currently the target-ppc tcg code only supports a single thread. You can specify more, but they're treated identically to multiple cores. On KVM we obviously can't support more threads than the hardware; if more are specified it will cause strange and cryptic errors. This patch clarifies the situation by giving a simple meaningful error if more threads are specified than we can support. Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-01-18PPC: KVM: Add support for EPR with KVMAlexander Graf
This patch links KVM EPR support to the existing TCG support we have now. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-01-18PPC: Provide zero SVR for -cpu e500mc and e5500Alexander Graf
Even though our -cpu types for e500mc and e5500 are no real CPUs that actually have version registers, a guest might still want to access said version register and that has to succeed for a guest to be happy. So let's expose a zero SVR value on E500_SVR SPR reads. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
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