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2013-03-22target-ppc: Rework get_physical_address()David Gibson
Currently get_physical_address() first checks to see if translation is enabled in the MSR, then in the translation on case switches on the mmu type. Except that for BookE MMUs, translation is always on, and so it has to switch in the "translation off" case as well and do the same thing as the translation on path for those MMUs. Plus, even translation off doesn't behave exactly the same on the various MMU types so there are further mmu type checks in the "translation off" path. As a first step to cleaning this up, this patch moves the switch on mmu type to the top level, then makes the translation on/off check just for those mmu types where it is meaningful. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle get_segment()David Gibson
The poorly named get_segment() function handles most of the address translation logic for hash-based MMUs. It has many ugly conditionals on whether the MMU is 32-bit or 64-bit. This patch splits the function into 32 and 64-bit versions, using the switch on mmu_type that's already in the caller (get_physical_address()) to select the right one. Most of the original function remains in mmu_helper.c to support the 6xx software loaded TLB implementations (cleaning those up is a project for another day). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle find_pte()David Gibson
32-bit and 64-bit hash MMU implementations currently share a find_pte function. This results in a whole bunch of ugly conditionals in the shared function, and not all that much actually shared code. This patch separates out the 32-bit and 64-bit versions, putting then in mmu-hash64.c and mmu-has32.c, and removes the conditionals from both versions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle pte_check()David Gibson
Currently support for both 32-bit and 64-bit hash MMUs share an implementation of pte_check. But there are enough differences that this means the shared function has several very ugly conditionals on "is_64b". This patch cleans things up by separating out the 64-bit version (putting it into mmu-hash64.c) and the 32-bit hash version (putting it in mmu-hash32.c). Another copy remains in mmu_helper.c, which is used for the 6xx software loaded TLB paths. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Move SLB handling into a mmu-hash64.cDavid Gibson
As a first step to disentangling the handling for 64-bit hash MMUs from the rest, we move the code handling the Segment Lookaside Buffer (SLB) (which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove address check for loggingDavid Gibson
One LOG_MMU statement in mmu_helper.c has an odd check on the effective address being translated. I can see no reason for this; I suspect it was a debugging hack from long ago. This patch removes it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Trivial cleanups in mmu_helper.cDavid Gibson
This removes the never-used pte64_invalidate() function, and makes ppcmas_tlb_check() static, since it's only used within that file. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson
The PowerPC 620 was the very first 64-bit PowerPC implementation, but hardly anyone ever actually used the chips. qemu notionally supports the 620, but since we don't actually have code to implement the segment table, the support is broken (quite likely in other ways too). This patch, therefore, removes all remaining pieces of 620 support, to stop it cluttering up the platforms we actually care about. This includes removing support for the ASR register, used only on segment table based machines. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22PPC/GDB: handle read and write of fpscrFabien Chouteau
Although the support of this register may be uncomplete, there are no reason to prevent the debugger from reading or writing it. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove CONFIG_PSERIES dependency in kvm.cDavid Gibson
target-ppc/kvm.c has an #ifdef on CONFIG_PSERIES, for the handling of KVM exits due to a PAPR hypercall from the guest. However, since commit e4c8b28cde12d01ada8fe869567dc5717a2dfcb7 "ppc: express FDT dependency of pSeries and e500 boards via default-configs/", this hasn't worked properly. That patch altered the configuration setup so that although CONFIG_PSERIES is visible from the Makefiles, it is not visible from C files. This broke the pseries machine when KVM is in use. This patch makes a quick and dirty fix, by removing the CONFIG_PSERIES dependency, replacing it with TARGET_PPC64 (since removing it entirely leads to type mismatch errors). Technically this breaks the build when configured with --disable-fdt, since that disables CONFIG_PSERIES on TARGET_PPC64. However, it turns out the build was already broken in that case, so this fixes pseries kvm without breaking anything extra. I'm looking into how to fix that build breakage, but I don't think that need delay applying this patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber
Move it to qom/cpu.h to avoid issues with include order. Change pc_acpi_smi_interrupt() opaque to X86CPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-08target-ppc: Move CPU aliases out of translate_init.cAndreas Färber
Move array of CPU aliases to cpu-models.c, alongside model definitions. This requires to zero-terminate the aliases array since ARRAY_SIZE() can no longer be used in translate_init.c then. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Report CPU aliases for QMPAndreas Färber
The QMP query-cpu-definitions implementation iterated over CPU classes only, which were getting less and less as aliases were extracted. Keep them in QMP as valid -cpu arguments even if not guaranteed stable. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: List alias names alongside CPU modelsAndreas Färber
Revert adding a separate -cpu ? output section for aliases and list them per CPU subclass. Requested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Make host CPU a subclass of the host's CPU modelAndreas Färber
This avoids assigning individual class fields and contributors forgetting to add field assignments in KVM-only code. ppc_cpu_class_find_by_pvr() requires the CPU model classes to be registered, so defer host CPU type registration to kvm_arch_init(). Only register the host CPU type if there is a class with matching PVR. This lets us drop error handling from instance_init. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix PPC_DUMP_SPR_ACCESS buildAndreas Färber
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0 conversion, insert the missing cpu_env arguments. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Synchronize FPU state with KVMDavid Gibson
Currently qemu does not get and put the state of the floating point and vector registers to KVM. This is obviously a problem for savevm, as well as possibly being problematic for debugging of FP-using guests. This patch fixes this by using new extensions to the ONE_REG interface to synchronize the qemu floating point state with KVM. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Add mechanism for synchronizing SPRs with KVMDavid Gibson
Currently when runing under KVM on ppc, we synchronize a certain number of vital SPRs to KVM through the SET_SREGS call. This leaves out quite a lot of important SPRs which are maintained in KVM. It would be helpful to have their contents in qemu for debugging purposes, and when we implement migration it will be vital, since they include important guest state that will need to be restored on the target. This patch sets up for synchronization of any registers supported by the KVM ONE_REG calls. A new variant on spr_register() allows a ONE_REG id to be stored with the SPR information. When we set/get information to KVM we also synchronize any SPRs so registered. For now we set this mechanism up to synchronize a handful of important registers that already have ONE_REG IDs, notably the DAR and DSISR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Change "POWER7" CPU aliasAndreas Färber
Let it resolve to v2.3 rather than v2.0. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix remaining microcontroller typos among modelsAndreas Färber
controler -> controller Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Split model definitions out of translate_init.cAndreas Färber
Now that model definitions only reference their parent type, model definitions are independent of the family definitions and can be compiled independently of TCG translation. Keep all #if defined(TODO) code local to cpu-models.c. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Update Coding Style for CPU modelsAndreas Färber
Drop the space in #if defined (TODO). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn descriptive CPU model comments into device descriptionsAndreas Färber
Fix microcontroller typo while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn descriptive CPU family comments into device descriptionsAndreas Färber
This gets rid of some more overly long comments that have lost most of their purpose now that in most cases there's only two functions left per CPU family. The class field is inherited by the actual CPU models, so override it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Set remaining fields on CPU family classesAndreas Färber
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Register all types for TARGET_PPCEMBAndreas Färber
Don't attempt to suppress registration of CPU types, since the criteria is actually a property of the class and should thus become a field. Since we can't check a field set in a class_init function before registering the type that leads to execution of that function, guard the -cpu class lookup instead and suppress exposing these classes in -cpu ? and in QMP. In case someone tries to hot-add an incompatible CPU via device_add, error out in realize. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Set instruction flags on CPU family classesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Introduce abstract CPU family typesAndreas Färber
Instead of assigning *_<family> constants, set .parent to a family type. Introduce a POWERPC_FAMILY() macro to keep type registration close to its implementation. This macro will need tweaking later. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Convert CPU definitionsAndreas Färber
Turn the array of model definitions into a set of self-registering QOM types with their own class_init. Unique identifiers are obtained from the combination of PVR, SVR and family identifiers; this requires all alias #defines to be removed from the list. Possibly there are some more left after this commit that are not currently being compiled. Prepares for introducing abstract intermediate CPU types for families. Keep the right-aligned macro line breaks within 78 chars to aid three-way merges. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Get model name from type nameAndreas Färber
We are about to drop the redundant name field along with ppc_def_t. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract POWER7 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 970 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 405GPe aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC8240 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC5200/MPC5200B aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC52xx aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx_HiP{3, 4} aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx aliases to *_HiP4Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliasesAndreas Färber
This depends on the fix for "G2leGP3" PVR. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e200 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e300 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC83xx aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e500v1/e500v2 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC85xx aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 604e aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 601/601v aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 603r aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>