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2012-06-09target-ppc: Unbreak kvm_ppc.c buildAndreas Färber
The file is located in target-ppc/, not hw/. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Anthony Liguori <anthony@codemonkey.ws> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini
Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-04Kill off cpu_state_reset()Andreas Färber
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-ppc: Let cpu_ppc_init() return PowerPCCPUAndreas Färber
Adapt e500 mpc8544ds machine accordingly. Turn cpu_init() into a static inline function returning CPUPPCState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Alexander Graf <agraf@suse.de>
2012-05-01target-ppc: Some support for dumping TLB_EMB TLBsFrançois Revol
Add mmubooke_dump_mmu(). TODO: Add printing of individual flags. Signed-off-by: François Revol <revol@free.fr> [agraf: fix coding style] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-05-01PPC: Fix up e500 cache size settingAlexander Graf
When initializing the e500 code, we need to expose its cache line size for user and system mode, while the mmu details are only interesting for system emulation. Split the 2 switch statements apart, allowing us to #ifdef out the mmu parts for user mode emulation while keeping all cache information consistent. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-04-15target-ppc/machine.c: Drop unnecessary ifdefsJuan Quintela
machine.c is only compiled for softmmu targets, so checks for !defined(CONFIG_USER_ONLY) are unnecessary and can be dropped. Signed-off-by: Juan Quintela <quintela@redhat.com> [AF: Use more verbose commit message suggested by PMM] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Init dcache and icache size for e500 user modeMeador Inge
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icache line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block. This is not correct because instructions like 'dcbz' need the dcache size initialized even for user mode. Signed-off-by: Meador Inge <meadori@codesourcery.com> Cc: Varun Sethi <Varun.Sethi@freescale.com> [AF: Simplify #ifdefs by using cache line size 32 for *-user as before] Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil
This changes nothing for other hosts. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: QOM'ify CPU resetAndreas Färber
Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Start QOM'ifying CPU initAndreas Färber
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: QOM'ify CPUAndreas Färber
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson
On target-ppc, our table of CPU types and features encodes the features as found on the hardware, regardless of whether these features are actually usable under TCG or KVM. We already have cases where the information from the cpu table must be fixed up to account for limitations in the emulation method we're using. e.g. TCG does not support the DFP and VSX instructions and KVM needs different numbering of the CPUs in order to tell it the correct thread to core mappings. This patch cleans up these hacks to handle emulation limitations by consolidating them into a pair of functions specifically for the purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [AF: Style and typo fixes, rename new functions and drop ppc_def_t arg] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Drop cpu_ppc_close()Andreas Färber
It is unused, so avoid QOM'ifying it unneededly. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15PPC: Fix TLB invalidation bug within the PPC interrupt handler.Mark Cave-Ayland
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07Replace Qemu by QEMU in commentsStefan Weil
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-15PPC: KVM: Synchronize regs on CPU dumpAlexander Graf
When we dump the CPU registers, there's a certain chance they haven't been synchronized with KVM yet, so we have to manually trigger that. This aligns the code with x86 and fixes a bug where the register state was bogus on invalid/unknown kvm exit reasons. Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15ppc: Correctly define POWERPC_INSNS2_DEFAULTMeador Inge
'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing the opcode table creation code to erroneously register 'eieio' and 'mbar' for the "default" processor: ** ERROR: opcode 1a already assigned in opcode table 16 *** ERROR: unable to insert opcode [1f-16-1a] *** ERROR initializing PowerPC instruction 0x1f 0x16 0x1a Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15PPC: Fix large page support in TCGNathan Whitehorn
Fix large page support in TCG. The old code would overwrite the large page table entry with the fake 4 KB one generated here whenever the ref/change bits were updated, causing it to point to the wrong area of memory. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Acked-by: David Gibson <david@gibson.drobpear.id.au> [agraf: fix whitespace, braces] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15PPC: Add PIR register to POWER7 CPUNathan Whitehorn
The POWER7 emulation is missing the Processor Identification Register, mandatory in recent POWER CPUs, that is required for SMP on at least some operating systems (e.g. FreeBSD) to function properly. This patch copies the existing PIR code from the other CPUs that implement it. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth
These instructions for loading and storing byte-swapped 64-bit values have been introduced in PowerISA 2.06. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15pseries: Don't try to munmap() a malloc()ed TCE tableDavid Gibson
For the pseries machine, TCE (IOMMU) tables can either be directly malloc()ed in qemu or, when running on a KVM which supports it, mmap()ed from a KVM ioctl. The latter option is used when available, because it allows the (frequent bottlenext) H_PUT_TCE hypercall to be KVM accelerated. However, even when KVM is persent, TCE acceleration is not always possible. Only KVM HV supports this ioctl(), not KVM PR, or the kernel could run out of contiguous memory to allocate the new table. In this case we need to fall back on the malloc()ed table. When a device is removed, and we need to remove the TCE table, we need to either munmap() or free() the table as appropriate for how it was allocated. The code is supposed to do that, but we buggily fail to initialize the tcet->fd variable in the malloc() case, which is used as a flag to determine which is the right choice. This patch fixes the bug, and cleans up error messages relating to this path while we're at it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-ppc: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14PPC: 405: Use proper CPU resetAlexander Graf
On ppc405ep there is a register that allows for software to reset the core, but not the whole system. Implement this reset using a reset interrupt. This gets rid of a bunch of #if 0'ed code. Reported-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-02-28target-ppc: Clean includesStefan Weil
Remove some include statements which are not needed. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-11ppc: remove unused variablesBlue Swirl
Fix this error: /src/qemu/target-ppc/helper.c: In function 'booke206_tlb_to_page_size': /src/qemu/target-ppc/helper.c:1296:14: error: variable 'tlbncfg' set but not used [-Werror=unused-but-set-variable] Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-02-02PPC: E500: Populate L1CFG0 SPRAlexander Graf
When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: Shrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500mc: Enable processor controlAlexander Graf
The e500mc implements Embedded.Processor Control, so enable it and thus enable guests to IPI each other. This makes -smp work with -cpu e500mc. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Implement msgsndAlexander Graf
This patch implements the msgsnd instruction. It is part of the Embedded.Processor Control specification and allows one CPU to IPI another CPU without going through an interrupt controller. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Implement msgclrAlexander Graf
This patch implements the msgclr instruction. It is part of the Embedded.Processor Control specification and clears pending doorbell interrupts on the current CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: Enable doorbell excp handlersAlexander Graf
We already had all the code available to have doorbell exceptions be handled properly. It was just disabled. Enable it, so we can rely on it. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: Add CPU feature for processor controlAlexander Graf
We're soon going to implement processor control features. Add the feature flag, so we're well prepared. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Add doorbell definesAlexander Graf
We're going to introduce doorbell instructions (called processor control in the spec) soon. Add some defines for easier patch readability later. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Add some more excp vectorsAlexander Graf
Our EXCP list is getting outdated. By now, 3 new exception vectors have been introduced. Update the list so we have everything at one place. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: move avail check to tlbweAlexander Graf
We can have TLBs that only support a single page size. This is defined by the absence of the AVAIL flag in TLBnCFG. If this is the case, we currently write invalid size info into the TLB, but override it on internal fault. Let's move the check over to tlbwe, so we don't have the AVAIL check in the hotter fault path. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Check for TLB overrunAlexander Graf
Our internal helpers to fetch TLB entries were not able to tell us that an entry doesn't even exist. Pass an error out if we hit such a case to not accidently pass beyond the TLB array. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Implement tlbilxAlexander Graf
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used to flush TLB entries. It's the recommended way of flushing in virtualized environments. So far we got away without implementing it, but Linux for e500mc uses this instruction, so we better add it :). Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Check for min/max TLB entry sizeAlexander Graf
When setting a TLB entry, we need to check if the TLB we're putting it in actually supports the given size. According to the 2.06 PowerPC ISA, a value that's out of range can either be redefined to something implementation dependent or we can raise an illegal opcode exception. We do the latter. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke: add tlbnps handlingAlexander Graf
When using MAV 2.0 TLB registers, we have another range of TLB registers available to read the supported page sizes from. Add SPR definitions for those and add a helper function that we can use to receive such a bitmap even when using MAV 1.0. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: allow NULL raddr in ppcmas_tlb_checkAlexander Graf
We might want to call the tlb check function without actually caring about the real address resolution. Check if we really should write the value back. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: rename msync to msync_4xxAlexander Graf
The msync instruction as defined today is only valid on 4xx cores, not on e500 which also supports msync, but treats it the same way as sync. Rename it to reflect that it's 4xx only. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500: msync is 440 only, e500 has real syncAlexander Graf
The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500mc: add missing IVORs to bitmapAlexander Graf
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE support too. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: Add IVOR 38-42Alexander Graf
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-02-02PPC: KVM: Update HIOR code to new interfaceAlexander Graf
Unfortunately the HIOR setting code slipped into upstream QEMU before it was pulled into upstream KVM. And since Murphy is always right, comments on the patches only emerged on the pull request leading to changes in the interface. So here's an update to the HIOR setting. While at it, I also relaxed it a bit since for HV KVM we can already run fine without and 3.2 works just fine with HV KVM but when not setting HIOR. We will only need this when running PAPR in PR KVM. Since we accidently changed the ABI and API along the way, we have to update the underlying kernel headers together with the code that uses it to not break bisectability. Signed-off-by: Alexander Graf <agraf@suse.de>
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