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AgeCommit message (Expand)Author
2016-06-23ppc: Disable huge page support if it is not available for main RAMThomas Huth
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt
2016-06-23ppc: Move exception generation code out of lineBenjamin Herrenschmidt
2016-06-23ppc: Turn a bunch of booleans from int to boolBenjamin Herrenschmidt
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt
2016-06-23ppc: Fix generation if ISI/DSI vs. HV modeBenjamin Herrenschmidt
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt
2016-06-23ppc: fix exception model for HV modeBenjamin Herrenschmidt
2016-06-23ppc: define a default LPCR valueBenjamin Herrenschmidt
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt
2016-06-22target-ppc: Fix rlwimi, rlwinm, rlwnm againRichard Henderson
2016-06-22ppc64: disable gen_pause() for linux-user modeLaurent Vivier
2016-06-20trace: split out trace events for target-ppc/ directoryDaniel P. Berrange
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova
2016-06-17spapr: Abstract CPU core device and type specific core devicesBharata B Rao
2016-06-17target-ppc: Fix rlwimi, rlwinm, rlwnmRichard Henderson
2016-06-17target-ppc: Bug in BookE wait instructionJakub Horak
2016-06-16os-posix: include sys/mman.hPaolo Bonzini
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth
2016-06-14ppc: Provide function to get CPU class of the host CPUThomas Huth
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth
2016-06-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt
2016-06-07ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processorsBenjamin Herrenschmidt
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt
2016-06-07target-ppc: fixup bitrot in mmu_helper.c debug statementsMark Cave-Ayland
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt
2016-06-07target-ppc/fpu_helper: Fix efscmp* instructions handlingTalha Imran
2016-06-05target-*: dfilter support for in_asmRichard Henderson
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt
2016-05-30ppc: Get out of emulation on SMT "OR" opsBenjamin Herrenschmidt
2016-05-30ppc: Fix sign extension issue in mtmsr(d) emulationMichael Neuling
2016-05-30ppc: Change 'invalid' bit mask of tlbiel and tlbieBenjamin Herrenschmidt
2016-05-30ppc: tlbie, tlbia and tlbisync are HV onlyBenjamin Herrenschmidt
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt
2016-05-30ppc: Remove MMU_MODEn_SUFFIX definitionsBenjamin Herrenschmidt
2016-05-27spapr_iommu: Finish renaming vfio_accel to need_vfioAlexey Kardashevskiy
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