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2013-07-29target-ppc/kvm.c: Rename 'dprintf' to 'DPRINTF'Peter Maydell
'dprintf' is the name of a POSIX standard function so we should not be stealing it for our debug macro. Rename to 'DPRINTF' (in line with a number of other source files.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: MORITA Kazutaka <morita.kazutaka@lab.ntt.co.jp> Acked-by: Richard Henderson <rth@twiddle.net> Acked-by: Kevin Wolf <kwolf@redhat.com> Message-id: 1375100199-13934-4-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori
QOM CPUState refactorings * Fix x86 cpu-add * Change KVM PMU behavior for 1.6 # gpg: Signature made Mon 29 Jul 2013 10:28:18 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Eduardo Habkost (2) and Andreas Färber (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Disable PMU CPUID leaf by default target-i386: Pass X86CPU object to cpu_x86_find_by_name() cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
2013-07-29pseries: savevm support with KVMAlexey Kardashevskiy
At present, the savevm / migration support for the pseries machine will not work when KVM is enabled. That's because KVM manages the guest's hash page table in the host kernel, so qemu has no visibility of it. This patch fixes this by using new kernel interfaces to extract and reinsert the guest's hash table during the migration process. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1374175984-8930-11-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29spapr-tce: make sPAPRTCETable a proper deviceAnthony Liguori
Model TCE tables as a device that's hooked up as a child object to the owner. Besides the code cleanup, we get a few nice benefits: 1) free actually works now (it was dead code before) 2) the TCE information is visible in the device tree 3) we can expose table information as properties such that if we change the window_size, we can use globals to keep migration working. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-6-git-send-email-aliguori@us.ibm.com [dwg: pseries: savevm support for PAPR TCE tables] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [alexey: ppc kvm: fix to compile] Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29target-ppc: Convert ppc cpu savevm to VMStateDescriptionAlexey Kardashevskiy
The savevm code for the powerpc cpu emulation is currently based around the old register_savevm() rather than register_vmstate() method. It's also rather broken, missing some important state on some CPU models. This patch completely rewrites the savevm for target-ppc, using the new VMStateDescription approach. Exactly what needs to be saved in what configurations has been more carefully examined, too. This introduces a new version (5) of the cpu save format. The old load function is retained to support version 4 images. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-2-git-send-email-aliguori@us.ibm.com [aik: ppc cpu savevm convertion fixed to use PowerPCCPU instead of CPUPPCState] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code. This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed". The reason for the failure is that CPUClass::kvm_fd is not yet initialized in the following call graph: ->x86_cpu_realizefn ->x86_cpu_apic_realize ->qdev_init ->device_set_realized ->device_reset (hotplugged == 1) ->apic_reset_common ->vapic_base_update ->kvm_apic_vapic_base_update This causes attempted KVM vCPU ioctls to fail. By contrast, in the non-hotplug case the APIC is reset much later, when the vCPU is already initialized. As a quick and safe solution, move the qemu_init_vcpu() call back into the targets' realize functions. Reported-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Acked-by: Igor Mammedov <imammedo@redhat.com> (for i386) Tested-by: Jia Liu <proljc@gmail.com> (for openrisc) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XMLAndreas Färber
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field. Use first_cpu for qSupported and qXfer:features:read: for now. Add a stub for xml_builtin. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber
Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber
This avoids polluting the global namespace with a non-prefixed macro and makes it obvious in the call sites that we return. Semi-automatic conversion using, e.g., sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c followed by manual tweaking for sparc's GET_REGA() and Coding Style. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26target-ppc: Move cpu_gdb_{read,write}_register()Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber
This moves setting the Program Counter from gdbstub into target code. Use vaddr type as upper-bound replacement for target_ulong. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-11target-ppc: Add POWER8 v1.0 CPU modelPrerna Saxena
This patch adds CPU PVR definition for POWER8, and enables QEMU to launch guests on POWER8 hardware. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org> Reviewed-by: Andreas Farber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11e600 core for MPC86xx processorsJulio Guerra
MPC86xx processors are based on the e600 core, which is not the case in qemu where it is based on the 7400 processor. This patch creates the e600 core and instantiates the MPC86xx processors based on it. Therefore, adding the high BATs, the SPRG 4..7 registers, which are e600-specific [1], and a HW MMU model (as 7400). This allows to define the MPC8610 processor too. Tested with a kernel using the HW TLB misses. [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf Signed-off-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber
x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-ppc: Change LOG_MMU_STATE() argument to CPUStateAndreas Färber
Choose CPUState rather than PowerPCCPU since doing a CPU() cast on the macro argument would hide type mismatches. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPUAndreas Färber
Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-ppc: Don't overuse ENV_GET_CPU()Andreas Färber
Commit b632a148b677b773ff155f9de840b37a653567b9 (target-ppc: QOM method dispatch for MMU fault handling) introduced a use of ENV_GET_CPU() inside target-ppc/ code. Use ppc_env_get_cpu() instead. Purely cosmetic, non-functional change to aid in locating and removing ENV_GET_CPU() usages. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber
A transition from CPUFooState to FooCPU can be considered safe, just like FooCPU::env access in the opposite direction. The only benefit of the FOO_CPU() casts would be protection against bogus CPUFooState pointers, but then surrounding code would likely break, too. This should slightly improve interrupt etc. performance when going from CPUFooState to FooCPU. For any additional CPU() casts see 3556c233d931ad5ffa46a35cb25cfc057732ebb8 (qom: allow turning cast debugging off). Reported-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-01PPC: Ignore writes to L2CRAlexander Graf
The L2CR register contains a number of bits that either impose configuration which we can't deal with or mean "something is in progress until the bit is 0 again". Since we don't model the former and we do want to accomodate guests using the latter semantics, let's just ignore writes to L2CR. That way guests always read back 0 and are usually happy with that. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Introduce an alias cache for faster lookupsAlexander Graf
When running QEMU with "-cpu ?" we walk through every alias for every target CPU we know about. This takes several seconds on my very fast host system. Let's introduce a class object cache in the alias table. Using that we don't have to go through the tedious work of finding our target class. Instead, we can just go directly from the alias name to the target class pointer. This patch brings -cpu "?" to reasonable times again. Before: real 0m4.716s After: real 0m0.025s Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Fix GDB read on code area for PPC6xxFabien Chouteau
On PPC 6xx, data and code have separated TLBs. Until now QEMU was only looking at data TLBs, which is not good when GDB wants to read code. This patch adds a second call to get_physical_address() with an ACCESS_CODE type of access when the first call with ACCESS_INT fails. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Add dump_mmu() for 6xxFabien Chouteau
"(qemu) info tlb" is a very useful tool for debugging, so I implemented the missing 6xx version. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> [agraf: fix printfs on hwaddr to PRI] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Introduce unrealizefn for PowerPCCPUAndreas Färber
Use it to clean up the opcode table, resolving a former TODO from Jocelyn. Also switch from malloc() to g_malloc(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc kvm: save cr registerAlexey Kardashevskiy
This adds a missing code to save CR (condition register) via kvm_arch_put_registers(). kvm_arch_get_registers() already has it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01ppc: do not register IABR SPR twice for 603eHervé Poussineau
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E(). Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Drop redundant flags assignments from CPU familiesAndreas Färber
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in some places for macrofied assignment to insns_flags2 field. PPC_NONE is defined as zero though and QOM classes are zero-initialized, so drop any pcc->insns_flags2 = PPC_NONE; assignments. PPC_NONE itself is still in use in translate.c. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01kvm/openpic: in-kernel mpic supportScott Wood
Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build, fix ppcemb] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Add non-kvm stub fileAlexander Graf
There are cases where a kvm provided function is called from generic hw code that doesn't know whether kvm is available or not. Provide a stub file which can provide simple replacement functions for those cases. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber
This allows to move the call into CPUState's realizefn. Therefore move the stub into libqemustub.a. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28kvm: Change cpu_synchronize_state() argument to CPUStateAndreas Färber
Change Monitor::mon_cpu to CPUState as well. Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-12KVM: PPC: Add dummy kvm_arch_init_irq_routing()Scott Wood
The common KVM code insists on calling kvm_arch_init_irq_routing() as soon as it sees kernel header support for it (regardless of whether QEMU supports it). Provide a dummy function to satisfy this. Unlike x86, PPC does not have one default irqchip, so there's no common code that we'd stick here. Even if you ignore the routes themselves, which even on x86 are not set up in this function, the initial XICS kernel implementation will not support IRQ routing, so it's best to leave even the general feature flags up to the specific irqchip code. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-18remove some double-includesMichael Tokarev
Some source files #include the same header more than once for no good reason. Remove second #includes in such cases. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-08PPC: Depend behavior of cmp instructions only on instruction encodingAlexander Graf
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it still behaves identical to what it does when SF is on. Remove the implicit difference in the code. Also, on most 32bit CPUs we should always treat the compare as 32bit compare, as the CPU will ignore the L bit. This is not true for e500mc, but that's up for a different patch. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-08PPC: Fix rldclAlexander Graf
The implementation for rldcl tried to always fetch its parameters from the opcode, even though the opcode was already passed in in decoded and different forms. Use the parameters instead, fixing rldcl. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Add read and write of PPR SPRAnton Blanchard
Recent Linux kernels save and restore the PPR across exceptions so we need to handle it. Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Fix invalid SPR read/write warningsAnton Blanchard
Invalid and privileged SPR warnings currently print the wrong address. While fixing that, also make it clear that we are printing both the decimal and hexadecimal SPR number. Before: Trying to read invalid spr 896 380 at 0000000000000714 After: Trying to read invalid spr 896 (0x380) at 0000000000000710 Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06PPC: Add MMU type for 2.06 with AMR but no TB pagesAlexander Graf
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB MMU capability from the MMU type mask, but not the AMR bit. This leads to us having a new MMU type that we don't check for in our MMU management functions. Add the new type, so that we don't have to worry about breakage there. We're not going to use the TCG MMU management in that case anyway. The long term fix for this will be to move all these MMU management functions to class callbacks. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-27target-ppc: slightly optimize lfiwaxAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-26target-ppc: add support for extended mtfsf/mtfsfi formsAurelien Jarno
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new W field to select the upper part of the FPCSR register. For that the helper is changed to handle 64-bit input values and mask with up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit marked as invalid anymore. Instead this is checked in the helper, which therefore needs to access to the insns/insns_flags2. They are added in the DisasContext struct. Finally change all accesses to the opcode fields through extract helpers, prefixed with FP for consistency. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate store doubleword pair instructionsAurelien Jarno
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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