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2014-04-08PPC: Add l1 cache sizes for 970 and above systemsAlexander Graf
Book3s_64 guests expect the L1 cache size in device tree, so let's give them proper values for all CPU types we support. This fixes a "not compliant" warning with sles11 guests on -M pseries for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-27target-ppc: MSR_POW not supported on POWER7/7+/8Anton Blanchard
Remove MSR_POW from the msr_mask for POWER7/7P/8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-27target-ppc: POWER7+ supports the MSR_VSX bitAnton Blanchard
Without MSR_VSX we die early during a Linux boot. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-27target-ppc: POWER8 supports iselAnton Blanchard
Add PPC_ISEL to insns_flags. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-27target-ppc: POWER8 supports the MSR_LE bitAnton Blanchard
Add MSR_LE to the msr_mask for POWER8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-20target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy
This flag will be used to decide whether to emulate some bits of H_SET_MODE hypercall because some are POWER8-only. While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already have it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-20target-ppc: Force CPU threads count to be a power of 2Bharata B Rao
PowerPC kernel expects the number of SMT threads in a core to be a power of 2. Since QEMU doesn't enforce this, it leads to an early guest kernel crash if invalid threads count is specified. Prevent this crash and make it a graceful exit from QEMU itself by validating the user-supplied threads count. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-20target-ppc: Fix overallocation of opcode tablesStuart Brady
create_new_table() should allocate 0x20 opc_handler_t pointers, but actually allocates 0x20 opc_handler_t structs. Fix this. Signed-off-by: Stuart Brady <sdb@zubnet.me.uk> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-20target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy
This resets SPR values to defaults on CPU reset. This should help with little-endian guests reboot issues. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber
Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Factor out cpu_generic_init()Andreas Färber
All targets using it gain the ability to set -cpu name,key=value,... options via the default TYPE_CPU CPUClass::parse_features() implementation. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber
Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-05target-ppc: spapr: e500: fix to use cpu_dt_idAlexey Kardashevskiy
This makes use of @cpu_dt_id and related API in: 1. emulated XICS hypercall handlers as they receive fixed CPU indexes; 2. XICS-KVM to enable in-kernel XICS on right CPU; 3. device-tree renderer. This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor can accept command-line CPU indexes again. This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment KVM CPU id and device tree ID are calculated using the same algorithm. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy
Normally CPUState::cpu_index is used to pick the right CPU for various operations. However default consecutive numbering does not always work for POWERPC. These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX and used to call KVM VCPU's ioctls. In order to achieve this, kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies cpu_index by the number of threads per core. This approach has disadvantages such as: 1. NUMA configuration stays broken after the fixup; 2. CPU-targeted commands from the QEMU Monitor do not work properly as CPU indexes have been fixed and there is no clear way for the user to know what the new CPU indexes are. This introduces a @cpu_dt_id field in the CPUPPCState struct which is initialized from @cpu_index by default and can be fixed later to meet the device tree requirements. This adds an API to handle @cpu_dt_id. This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id is calculated in ppc_cpu_realize(). This will be used later in machine code. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Instruction FlagTom Musta
This patch adds a flag that will be used to tag the Altivec instructions introduced in Power ISA Version 2.07. The flag is added to Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Load QuadwordTom Musta
This patch adds the Book I (user space) Load Quadword (lq) instruction. This instruction was introduced into Book I in Power ISA V2.07. Previous versions of the architecture supported this as a privileged instruction. Previous versions of the architecture also did not support Little Endian mode. Note that this patch also adds the PPC_64BX flag to the Power8 model, which enables the lq instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta
This patch adds a flag to identify the load/store quadword instructions that are introduced with Power ISA 2.07. The flag is added to the Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta
This patch adds support for the Target Address Register (TAR) to the Power8 model. Because supported SPRs are typically identified in an init_proc_*() function and because the Power8 model is currently just using the init_proc_POWER7() function, a new init_proc_POWER8() function is added and plugged into the P8 model. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for bctarTom Musta
This patch adds a flag for the bctar instruction. This instruction is being introduced via Power ISA 2.07. Also, the flag is added to the Power8 machine model since the P8 processor supports this instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Enable frsqrtes on Power7 and Power8Tom Musta
The frsqrtes instruction was introduced prior to ISA 2.06 and is support on both the Power7 and Power8 processors. However, this instruction is handled as illegal in the current QEMU emulation machines. This patch enables the existing implemention of frsqrtes in the P7 and P8 machines. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta
This patch adds a flag for Floating Point Test instructions that were introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix and enable fri[mnpz]Tom Musta
The fri* series of instructions was introduced prior to ISA 2.06 and is supported on Power7 and Power8 hardware. However, the instruction is still considered illegal in the P7 and P8 QEMU emulation models. This patch enables these instructions for the P7 and P8 machines. Also, the existing helper is modified to correctly handle some of the boundary cases (NaNs and the inexact flag). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta
This patch adds a flag for the floating point conversion instructions introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta
This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta
This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 bpermd InstructionTom Musta
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta
This patch adds a flag to identify those VSX instructions that are new to Power ISA V2.07. The flag is added to the Power 8 processor initialization so that the P8 models understand how to decode and emulate instructions in this category. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRLAlexey Kardashevskiy
The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL - no 32 S 152 00100 11000 CTRL yes - 32 S According to this chart, the hypervisor's CTRL (#152) does not support reading, the user-space's CTRL (UCTRL, #136) does not support writing. This replaces unsupported operations with the default SPR_NOACCESS hook. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05PPC: KVM: add support for LPCRGreg Kurz
The LPCR special purpose register was introduced with the PowerPC 970MP family. This patch initializes LPCR for the following families: - 970 MP - POWER5+ - POWER7 - POWER8 Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05PPC: KVM: fix "set one register"Alexey Kardashevskiy
Due to missing @one_reg_id assignment in _spr_register(), the kvm_get_one_reg/kvm_set_one_reg API has never really been working. This reenables the API by assigning the @one_reg_id field in the SPR descriptor. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix Authority Mask Register init valueAlexey Kardashevskiy
The existing default value (-1) of the AMR register forbids data access to all 32 classes. Since the guest linux does not change this register, we end up with the guest hanging right after switching from the real to protected mode. This sets the default AMR value to zero what enables data access for all classes. The only reason for not hitting this bug before is that kvm_arch_put_registers() did not put any SPR to KVM due to missing assignment of @one_reg_id in _spr_register() (which is going to be fixed by a separate patch). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove unsupported SPRs from 970 and P5+Alexey Kardashevskiy
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5 bookIV nor PowerISA 2.04, the numbers assigned to them are not defined either so remove them. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8Alexey Kardashevskiy
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so remove it from POWER7/8 class as it is "S" (server) category. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove powerpc 970gxAlexey Kardashevskiy
The 970GX definition was added in 2007 and it made sense then but this version has never been released to the markets and it does not exist in the real world so there is no point in emulating it. This removes 970GX. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix LPCR SPR numberAlexey Kardashevskiy
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of 316. This fixes the definition of LPCR SPR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix compile error when PPC_DUMP_CPU is enabledAlexey Kardashevskiy
Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU breaks compile. This fixes compiler errors. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-02-13target-ppc: Make ppc40x CPUs available in ppcembAndreas Färber
Not only 44x CPUs (BookE) but also 40x CPUs can run with 1k page size. Move the criteria to a central inline function to avoid repetition and #ifdef'fery. Update qom-test to no longer exempt them. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add MSR VSX and Associated ExceptionTom Musta
This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Declare and Enable VSXTom Musta
This patch adds the flag POWERPC_FLAG_VSX to the list of defined flags and also adds this flag to the list of supported features of the Power7 and Power8 CPUs. Additionally, the VSX instructions are added to the list of TCG-enabled instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25spapr: Use DeviceClass::fw_name for device tree CPU nodeAndreas Färber
Instead of relying on cpu_model, obtain the device tree node label per CPU. Use DeviceClass::fw_name as source. Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN". As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name, obsoleting sPAPREnvironment::cpu_model, and spapr_create_fdt_skel() can drop its cpu_model argument. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Fill in OpenFirmware names for some PowerPCCPU familiesAndreas Färber
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+. Note that POWER5+ and POWER7+ are intentionally lacking the '+', so the lack of a POWER7P family constitutes no problem. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: dump-guest-memory supportAneesh Kumar K.V
This patch add support for dumping guest memory using dump-guest-memory monitor command. Before patch: (qemu) dump-guest-memory testcrash this feature or command is not currently supported (qemu) After patch: (qemu) dump-guest-memory testcrash (qemu) crash was able to read the file crash> bt PID: 0 TASK: c000000000c0d0d0 CPU: 0 COMMAND: "swapper/0" R0: 0000000028000084 R1: c000000000cafa50 R2: c000000000cb05b0 R3: 0000000000000000 R4: c000000000bc4cb0 R5: 0000000000000000 R6: 001efe93b8000000 R7: 0000000000000000 R8: 0000000000000000 R9: b000000000001032 R10: 0000000000000001 R11: 0001eb2117e00d55 .... ... NOTE: Currently crash tools doesn't look at ELF notes in the dump on ppc64. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25PPC: Fix L2CR write accessesAlexander Graf
Commit 2345f1c01 was supposed to render L2CR writes into noops. Instead, it made them illegal instruction traps which apparently didn't confuse XNU, but can easily confuse other OSs. Fix it up by actually doing nothing when we write to L2CR. Reported-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Julio Guerra <guerr@julio.in>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-02target-ppc: POWER7 supports the MSR_LE bitAnton Blanchard
Add MSR_LE to the msr_mask for POWER7. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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