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path: root/target-ppc/translate/vsx-ops.inc.c
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2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-10-28target-ppc: Add xvcmpnesp, xvcmpnedp instructionsSwapnil Bokade
xvcmpnedp[.]: VSX Vector Compare Not Equal Double-Precision xvcmpnesp[.]: VSX Vector Compare Not Equal Single-Precision Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-28target-ppc: add xscmp[eq,gt,ge,ne]dp instructionsSandipan Das
xscmpeqdp: VSX Scalar Compare Equal Double-Precision xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision xscmpnedp: VSX Scalar Compare Not Equal Double-Precision Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-28target-ppc: implement xxbr[qdwh] instructionNikunj A Dadhania
Add required helpers (GEN_XX2FORM_EO) for supporting this instruction. xxbrh: VSX Vector Byte-Reverse Halfword xxbrw: VSX Vector Byte-Reverse Word xxbrd: VSX Vector Byte-Reverse Doubleword xxbrq: VSX Vector Byte-Reverse Quadword Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mtvsrws instructionRavi Bangoria
mtvsrws: Move To VSR Word & Splat Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add stxvb16x instructionNikunj A Dadhania
stxvb16x: Store VSX Vector Byte*16 Vector (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Store results in following: Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add lxvb16x instructionNikunj A Dadhania
lxvb16x: Load VSX Vector Byte*16 Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Vector load results in (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add stxvh8x instructionNikunj A Dadhania
stxvh8x: Store VSX Vector Halfword*8 Vector (16-bit elements): +------+------+------+------+------+------+------+------+ | 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 | +------+------+------+------+------+------+------+------+ Store results in following: Big-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 | +-------+-------+-------+-------+-------+-------+-------+-------+ Little-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 | +-------+-------+-------+-------+-------+-------+-------+-------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Tweak commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add lxvh8x instructionNikunj A Dadhania
lxvh8x: Load VSX Vector Halfword*8 Big-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 | +-------+-------+-------+-------+-------+-------+-------+-------+ Little-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 | +-------+-------+-------+-------+-------+-------+-------+-------+ Vector load results in (16-bit elements): +------+------+------+------+------+------+------+------+ | 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 | +------+------+------+------+------+------+------+------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Tweak to commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mtvsrdd instructionRavi Bangoria
mtvsrdd: Move To VSR Double Doubleword Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mfvsrld instructionRavi Bangoria
mfvsrld: Move From VSR Lower Doubleword Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add stxsi[bh]x instructionNikunj A Dadhania
stxsibx - Store VSX Scalar as Integer Byte Indexed stxsihx - Store VSX Scalar as Integer Halfword Indexed Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add lxsi[bw]zx instructionNikunj A Dadhania
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add xxspltib instructionNikunj A Dadhania
xxspltib: VSX Vector Splat Immediate Byte Copy the immediate byte in each byte of target VSR Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt
Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-24 12:52:15 +0000