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2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-05target-ppc: Use Additional Temporary in stqcx CaseTom Musta
Per Alex Graf's suggestion, the recently added case to gen_conditional_store for stqcx should use an additional temporary when accessing the second doubleword. This avoids the mutation of the EA argument to the function, which is counter intuitive. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc/translate.c: Use ULL suffix for 64 bit constantsPeter Maydell
64 bit constants need the "ULL" suffix, not just "UL", because on 32 bit platforms 'long' is not large enough and this will cause a compiler warning. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Permute and Exclusive ORTom Musta
This patch adds the Vector Permuate and Exclusive OR (vpermxor) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector SHA Sigma InstructionsTom Musta
This patch adds the Vector SHA Sigma instructions introduced in Power ISA Version 2.07: - Vector SHA-512 Sigma Doubleword (vshasigmad) - Vector SHA-256 Sigma Word (vshasigmaw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: AES InstructionsTom Musta
This patch adds the Vector AES instructions introduced in Power ISA Version 2.07: - Vector AES Cipher (vcipher) - Vector AES Cipher Last (vcipherlast) - Vector AES Inverse Cipher (vncipher) - Vector AES Inverse Cipher Last (vncipherlast) - Vector AES SubBytes (vsbox) Note that the implementation of vncipher deviates from the RTL in ISA V2.07. However it does match the verbal description in the third paragraph. The RTL will be fixed in ISA V2.07B. The implementation here has been tested against actual P8 hardware. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Binary Coded Decimal InstructionsTom Musta
This patch add the Binary Coded Decimal instructions bcdadd. and bcdsub. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Polynomial Multiply SumTom Musta
This patch adds the Vectory Polynomial Multiply Sum instructions introduced in Power ISA Version 2.07: - Vectory Polynomial Multiply Sum Byte (vpmsumb) - Vectory Polynomial Multiply Sum Halfword (vpmsumh) - Vectory Polynomial Multiply Sum Word (vpmsumw) - Vectory Polynomial Multiply Sum Doubleword (vpmsumd) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Gather Bits by BytesTom Musta
This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd) instruction which is introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Doubleword ComparesTom Musta
This patch adds the Vector Compare Doubleword instructions introduced by Power ISA Version 2.07: - Vector Compare Equal to Unsigned Doubleword (vcmpequd) - Vector Compare Greater Than Signed Doubleword (vcmpgtsd) - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud) These instructions are encoded with bit 31 set to 1 and so are duals with vcmpeqfp, vcmpgtfp and vcmpbfp respectively. The helper macro for integer compares is enhanced to account for 64-bit operands. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vbpermq InstructionTom Musta
This patch adds the Vector Bit Permute Quadword (vbpermq) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Quadword Addition and SubtracationTom Musta
This patch adds the Vector Quadword Addition and Subtraction instructions introduced in Power ISA Version 2.07: - Vector Add Unsigned Quadword Modulo (vadduqm) - Vector Add & Write Carry Unsigned Quadword (vaddcuq) - Vector Add Extended Unsigned Quadword (vaddeuqm) - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq) - Vector Subtract Unsigned Quadword Modulo (vsubuqm) - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq) - Vector Subtract Extended Unsigned Quadword (vsubeuqm) - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift InstructionsTom Musta
This patch adds the vector doublword rotate and shift instructions introduced in Power ISA Version 2.07: - Vector Rotate Left Doubleword instruction (vrld) - Vector Shift Left Doubleword (vsld) - Vector Shift Right Doubleword (vsrd) - Vector Shift Right Algegbraic Doubleword (vsrad) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Merge InstructionsTom Musta
This patch adds the Vector Merge Even Word (vmrgew) and Vector Merge Odd Word (vmrgow) instructions introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta
This patch adds the Unpack Signed Word instructions introduced in Power ISA Version 2.07: - Vector Unpack High Signed Word (vupkusw) - Vector Unpack Low Signed Word (vupklsw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta
This patch adds the Vector Pack Doubleword instructions introduced in Power ISA Version 2.07: - Vector Pack Signed Doubleword Signed Saturate (vpksdss) - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus) - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum) - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta
This patch adds the Vector Minimum and Maximum Doubleword instructions that are introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta
This patch adds the Vector Population Count instructions introduced in Power ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta
This patch adds the Vector Count Leading Zeroes instructions introduced in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vmuluw InstructionTom Musta
This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm) instruction. The existing VARITH_DO macro is re-used to (trivially) instantiate the helper code. Since bits 21-31 of any vmuluwm instruction is 137, the instruction is coded as a dual to vmulouw (bits 21-31 = 136). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta
This patch adds the Multilpy Even/Odd Word instructions that are introduced in Power ISA Version 2.07: - Vector Multiply Even Unsigned Word (vmuleuw) - Vector Multiply Even Signed Word (vmulesw) - Vector Multiply Odd Unsigned Word (vmulouw) - Vector Multiply Odd Signed Word (vmulosw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword ModuloTom Musta
This patch adds two Altivec unsigned doublword modulo instructions that are introduced in Power ISA Version V2.07: - vaddudm : Vector Add Unsigned Doubleword Modulo - vsubudm : Vector Subtrace Unsigned Doubleword Modulo Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Logical InstructionsTom Musta
This patch adds the Vector Logical Instructions that are introduced in Power ISA Version 2.07: veqv, vnand and vorc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Support for R-Form Dual InstructionsTom Musta
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31 (aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc bit. QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes. This patch introduces a generator macro that injects an auxiliary handler which decodes both bits 21 and 31 and invokes one of four standard handlers. Since the instructions are not, in general, from the same version of the ISA, two sets of PPC_*/PPC2_* flags are supported. This patch also introduces a macro to insert two entries into the opcode table -- one for bit 21 equal to 0 and one for bit 21 equal to 1. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Opcode Macro for VX Form InstructionsTom Musta
This patch adds a macro to insert an entry into the opcode table for Altivec Power ISA Version 2.07 instructions. The macro is similar to the GEN_VXFORM macro except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than PPC_ALTIVEC. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Support for Dual Altivec InstructionsTom Musta
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31 (aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses bits 0-5 and 21-30 for opcodes and not bit 31. This patch introduces macros that will handle this situation by injecting an auxiliary handler which decodes bit 31 in invokes one of two standard handlers. Since the instructions are not, in general, from the same version of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add GEN_VXFORM3Tom Musta
This patch adds generator macro for Altivec instructions that have 3 source AVR operands. The macro is similar to the 2 operand form. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Store Quadword ConditionalTom Musta
This patch adds the Store Quadword Conditionl (stqcx.) instruction which is introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> [agraf: fix compile error when !TARGET_PPC64] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Load Quadword and ReserveTom Musta
This patch adds the Load Quadword and Reserve (lqarx) instruction, which is new in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Store QuadwordTom Musta
This patch adds support for the Store Quadword instruction in user mode. Prior to Power ISA 2.07, stq was legal only in privileged mode. Support for Little Endian mode is also new in ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Load QuadwordTom Musta
This patch adds the Book I (user space) Load Quadword (lq) instruction. This instruction was introduced into Book I in Power ISA V2.07. Previous versions of the architecture supported this as a privileged instruction. Previous versions of the architecture also did not support Little Endian mode. Note that this patch also adds the PPC_64BX flag to the Power8 model, which enables the lq instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add is_user_mode Utility RoutineTom Musta
This patch adds a boolean function is_user_mode that can be re-used in translation code that is sensitive to the MSR[PR] (user-mode) state. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add bctar InstructionTom Musta
This patch adds the Branch Conditional to Address Register (bctar) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix xxpermdi When T==A or T==BTom Musta
The existing implementation of xxpermdi is defective if the target VSR is also a source VSR. This patch fixes the defect in this case but also preserves the simpler, two TCG operation implementation when the target is not once of the two sources. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: add extended opcodes for dcbt/dcbtstCédric Le Goater
The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 00000000000a7cc0 <memrchr>: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addi r2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addi r7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 .... which breaks grep, and other commands, in TCG mode : invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0 This patch adds the extended opcodes for dcbt/dcbtst as no-ops just like the 'dcbt' instruction. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 lfiwzx InstructionTom Musta
This patch adds the Load Floating Point as Integer Word and Zero Indexed (lfiwzx) instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 ftsqrtTom Musta
This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 ftdiv InstructionTom Musta
This patch adds the Floating Point Test for Divide instruction which was introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 fcfid[u][s] InstructionsTom Musta
This patch adds the fcfids, fcfidu and fcfidus instructions which were introduced in Power ISA 2.06B. A common macro is provided to eliminate repetitious code, and the existing fcfid instruction is refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 Float to Integer InstructionsTom Musta
This patch adds the four floating point to integer conversion instructions introduced by Power ISA V2.06: - Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward Zero (fctiwuz) - Floating Convert to Integer Doubleword Unsigned (fctidu) - Floating Convert to Integer Doubleword Unsigned with Round Toward Zero (fctiduz) A common macro is developed to eliminate repetitious code. Existing instructions are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 stbcx. and sthcx. InstructionsTom Musta
This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 lbarx, lharx InstructionsTom Musta
This patch adds the byte and halfword variants of the Load and Reserve instructions. Since there is much commonality among all forms of Load and Reserve, a macro is provided and the existing implementations of lwarx and ldarx are refactoried to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 divwe[o] InstructionsTom Musta
This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 divweu[o] InstructionsTom Musta
This patch addes the Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta
This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta
This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 bpermd InstructionTom Musta
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Scalar Non-Signalling ConversionsTom Musta
This patch adds the non-signalling scalar conversion instructions: - VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision Non-Signalling (xscvdpspn) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Scalar Round to Single PrecisionTom Musta
This patch adds the VSX Scalar Round to Single Precision (xsrsp) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Floating Merge Word InstructionsTom Musta
This patch adds the Floating Merge Even Word (fmrgew) and Floating Merge Odd Word (fmrgow) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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