Age | Commit message (Collapse) | Author |
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Fixes clang errors:
CC ppc-softmmu/translate.o
/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3748:28: note: instantiated from:
if (likely(read_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
if (likely(write_cb != SPR_NOACCESS)) {
/src/qemu/target-ppc/translate.c:3903:29: note: instantiated from:
if (likely(write_cb != SPR_NOACCESS)) {
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Invalid opcode messages can be perfectly normal, for example if this
code is never executed. Don't print an error message on the console,
but keep the message in the log for debugging purposes.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Remove a temp local variable and a jump by computing a mask with shifts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,
f40d753718c72693c5f520f0d9899f6e50395e94,
96555a96d724016e13190b28cffa3bc929ac60dc and
3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile.
Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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We define inline as always_inline.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
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We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed. It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
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Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Baojun Wang <wangbj@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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For 32-bit PPC targets, we translated:
evmergelo rX, rX, rY
as:
rX-lo = rY-lo
rX-hi = rX-lo
which is wrong, because we should be transferring rX-lo first. This
problem is fixed by swapping the order in which we write the parts of
rX.
Similarly, we translated:
evmergelohi rX, rX, rY
as:
rX-lo = rY-hi
rX-hi = rX-lo
In this case, we can't swap the assignment statements, because that
would just cause problems for:
evmergelohi rX, rY, rX
Instead, we detect the first case and save rX-lo in a temporary
variable:
tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp
These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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uninitialized
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Do this so other pieces of code can make decisions based on the
capabilities of the CPU we're emulating.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: malc <av1474@comtv.ru>
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
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This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
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While searching PC, always store the pc of a new instruction.
Instructions that didn't generate tcg code (such as nop) prevented the
next one to be referenced.
Based on patch for target-alpha, r6930.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
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Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
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Mtfsf can have the L bit set, so all the register contents get stored
in FPSCR. Linux uses it, so let's implement it.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
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Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB
flush opcode only flushes an entry for the CPU it runs on, not across
all CPUs in the system.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
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In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.
This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later.
This is required for Linux to run on PPC64.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
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- use ctz32 instead of ffs - 1
- small optimisation of mtcrf
- add the name of both opcodes
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
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Noticed by Alexander Graf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
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When the CPU is in little endian mode, it should load values from RAM
in byte swapped manner. This check is in all the ld and st functions,
but misspelled in gen_qemu_ld32s.
This patch fixes the misspelling and makes ppc64 Linux happier.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6654 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6629 c046a42c-6fe2-441c-8c8c-71466251a162
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Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
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Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
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