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2008-11-30target-ppc: convert external load/store instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5831 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert load/store with reservation instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5830 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert lscbx instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert load/store string instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert icbi instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert dcbz instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert load/store multiple instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27target-ppc: convert POWER2 load/store instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27target-ppc: convert SPE load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-24target-ppc: convert altivec load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23target-ppc: convert FPU load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5786 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22target-ppc: convert exceptions generation to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15ppc: convert integer load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5493 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13Use float32/64 instead of float/doubleaurel32
The patch below uses the float32 and float64 types instead of the float and double types in the PPC code. This doesn't change anything when using softfloat-native as the types are the same, but that helps compiling the PPC target with softfloat. It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and use them instead of identical unions that are defined in numerous places. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-22Add new sane low-level memory accessors for PowerPC that do properj_mayer
size or zero extension, with homogenous names. Fix load & store strings: those are now endian-sensitive, by definition. Fix dcbz: must always align the target address to a cache line boundary. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3719 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-19PowerPC instruction fixes:j_mayer
- hrfid is part of the hypervisor extension - fix stfiwx naming git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3705 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12Allow use of SPE extension by all PowerPC targets,j_mayer
adding gprh registers to store GPR MSBs when GPRs are 32 bits. Remove not-needed-anymore ppcemb-linux-user target. Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12More PowerPC target -1 usage fixes (reservation address).j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3627 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27Fix endianness bug for PowerPC stfiwx instruction.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3456 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07Implement PowerPC Altivec load & stores, used by Apple firmware for memcpy.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07PowerPC target coding style fixes.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07PowerPC target optimisations: make intensive use of always_inline.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3347 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-04Make PowerPC cache line size implementation dependant.j_mayer
Implement dcbz tunable cache line size for PowerPC 970. Make hardware reset vector implementation dependant. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30Improve single-precision floats load & stores:j_mayer
as the PowerPC registers only store double-precision floats, use float64_to_float32 & float32_to_float64 to do the appropriate conversion. Implement stfiwx. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3280 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Rework PowerPC exceptions model to make it more versatile:j_mayer
* don't use exception vectors as the exception number. Use vectors numbers as defined in the PowerPC embedded specification instead and extend this model to cover all emulated PowerPC variants exceptions. * add some missing exceptions definitions, from PowerPC 2.04 specification and actual PowerPC implementations. * add code provision for hypervisor exceptions handling. * define exception vectors and prefix in CPUPPCState to emulate BookE exception vectors without any hacks. * define per CPU model valid exception vectors. * handle all known exceptions in user-mode only emulations. * fix hardware interrupts priorities in most cases. * change RET_EXCP macros name into GEN_EXCP as they don't return. * do not stop translation on most instructions that are not defined as context-synchronizing in PowerPC specification. * fix PowerPC 64 jump targets and link register update when in 32 bits mode. * Fix PowerPC 464 and 464F definitions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3261 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17PowerPC flags update/use fixes:j_mayer
- fix confusion between overflow/summary overflow, as reported by S Bansal. - reset carry in addic. optimized case (as it was already done in addic). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3179 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17Coding style fixes in PowerPC related code (no functional change):j_mayer
- avoid useless blanks at EOL. - avoid tabs. - fix wrapping lines on 80 chars terminals. - add missing ';' at macros EOL to avoid confusing auto-identers. - fix identation. - Remove historical macros in micro-ops (PARAM, SPARAM, PPC_OP, regs) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3178 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-24Code provision for new PowerPC embedded target support with:j_mayer
- 1 kB page size - 64 bits GPR - 64 bits physical address space - SPE extension support. Change TARGET_PPCSPE into TARGET_PPCEMB git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23Add missing PowerPC 64 instructionsj_mayer
PowerPC 64 fixes. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2530 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-20PowerPC 2.03 SPE extension - first pass.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2519 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-18As icbi is not a priviledge instruction and is treated as a load by the MMUj_mayer
it needs to be implemented for every MMU translation mode. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2492 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-17Make it safe to use 64 bits GPR and/or 64 bits host registers.j_mayer
For "symetry", add 64 bits versions of all modified functions. As a side effect, add a lot of code provision for PowerPC 64 support. Move overflow and carry checks in common routines for simple cases. Add isel and popcntb instructions from PowerPC 2.03 specification. Remove remaining micro-operations helpers prototypes from op.c. Fix XER_BC field to be 7 bits long. Add power management support for PowerPC 603 & 604. Fix compilation warnings. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2482 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-07Great PowerPC emulation code resynchronisation and improvments:j_mayer
- Add status file to make regression tracking easier - Move all micro-operations helpers definitions into a separate header: should never be seen outside of op.c - Update copyrights - Add new / missing PowerPC CPU definitions - Add definitions for PowerPC BookE - Add support for PowerPC 6xx/7xx software driven TLBs Allow use of PowerPC 603 as an example - Add preliminary code for POWER, POWER2, PowerPC 403, 405, 440, 601, 602 and BookE support - Avoid compiling priviledged only resources support for user-mode emulation - Remove unused helpers / micro-ops / dead code - Add instructions usage statistics dump: useful to figure which instructions need strong optimizations. - Micro-operation fixes: * add missing RETURN in some micro-ops * fix prototypes * use softfloat routines for all floating-point operations * fix tlbie instruction * move some huge micro-operations into helpers - emulation fixes: * fix inverted opcodes for fcmpo / fcmpu * condition register update is always to be done after the whole instruction has completed * add missing NIP updates when calling helpers that may generate an exception - optimizations and improvments: * optimize very often used instructions (li, mr, rlwixx...) * remove specific micro-ops for rarely used instructions * add routines for addresses computations to avoid bugs due to multiple different implementations * fix TB linking: do not reset T0 at the end of every TB. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2473 c046a42c-6fe2-441c-8c8c-71466251a162
2005-04-23This patch adds little-endian mode support to PPC emulation.bellard
This is needed by OS/2 and Windows NT and some programs like VirtualPC. This patch has been tested using OS/2 bootloader (thanks to Tero Kaarlela). (Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1379 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-0364 bit target supportbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1195 c046a42c-6fe2-441c-8c8c-71466251a162
2004-05-21PowerPC merge: real time TB and decrementer - faster and simpler exception ↵bellard
handling (Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@841 c046a42c-6fe2-441c-8c8c-71466251a162
2004-02-21lwarx fix (Jocelyn Mayer)bellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@629 c046a42c-6fe2-441c-8c8c-71466251a162
2004-01-18PowerPC merge (Jocelyn Mayer)bellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@566 c046a42c-6fe2-441c-8c8c-71466251a162
2004-01-04suppressed explicit access type and use the exception routine to infer it ↵bellard
from the micro operation git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@529 c046a42c-6fe2-441c-8c8c-71466251a162
2004-01-04PowerPC system emulation (Jocelyn Mayer) - modified patch to use new TLB apibellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@528 c046a42c-6fe2-441c-8c8c-71466251a162
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