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2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-10target-ppc: convert most SPE integer instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01target-ppc: optimize popcntbaurel32
Suggested by Andrzej Zaborowski. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5592 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01target-ppc: convert 405 MAC instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5591 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01target-ppc: convert arithmetic functions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: convert logical instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: convert crf related instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: Convert XER accesses to TCGaurel32
Define XER bits as a single register and access them individually to avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit registers). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-14PPC: convert effective address computation to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01target-ppc: fix computation of XER.{CA, OV} in addme, subfmeaurel32
(Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5380 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01target-ppc: fix mullw/mullwoaurel32
Based on patch by Julian Seward. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5379 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24Revert commits 5082 and 5083aurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5084 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24PPC: Switch a few instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25Fix off-by-one unwinding error.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07Revert revisions r4168 and r4169. That's work in progress, not ready for ↵aurel32
trunk yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07Always enable precise emulation when softfloat is usedaurel32
The patch below changes the way to enable softfloat on the PPC target. It is now enabled when softfloat is used. The rationale behind this change is that persons who want precise emulation prefer precision over emulation speed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13Math functions helper for CONFIG_SOFTFLOAT=yesaurel32
The patch below adds isfinite() and isnormal() functions which can work with float64 type, used when CONFIG_SOFTFLOAT=yes. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4048 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13Use float32/64 instead of float/doubleaurel32
The patch below uses the float32 and float64 types instead of the float and double types in the PPC code. This doesn't change anything when using softfloat-native as the types are the same, but that helps compiling the PPC target with softfloat. It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and use them instead of identical unions that are defined in numerous places. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-10mtfsf: fix FPSCR_VX and FPSCR_FEX computationaurel32
The patch below fixes the computation of FPSCR_VX and FPSCR_FEX when using the mtfsf instruction. As stated in the PowerPC manual the mtfsf instruction can't alter those bit, and thus it should always be computed. Acked by Jocelyn Mayer. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4034 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24Fix incorrect debug prints (reported by Paul Brook).j_mayer
Remove obsolete / duplicated debug prints and improve output consistency. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23Revert foolish patch.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-23Fix ppc32 register dumps on 64-bit hosts.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.j_mayer
Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-16Always make PowerPC hypervisor mode memory accesses and instructionsj_mayer
available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator. Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3654 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12Allow use of SPE extension by all PowerPC targets,j_mayer
adding gprh registers to store GPR MSBs when GPRs are 32 bits. Remove not-needed-anymore ppcemb-linux-user target. Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12Fix usage of the -1 constant in the PowerPC target code:j_mayer
fix invalid size casts and/or sign-extensions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3626 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11fixed invalid typebellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11Fix POWER abs & abso computation.j_mayer
Fix PowerPC SPE evabs & evneg (thanks to Fabrice Bellard for reporting the bug) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3575 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11Optimize PowerPC overflow flag computation in most useful cases.j_mayer
Use the same routines to check overflow for addo, subfo and PowerPC 405 multiply and add cases. Fix carry reset in addme(o) and subfme(o) cases. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3574 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-04PowerPC 601 need specific callbacks for its BATs setup.j_mayer
Implement PowerPC 601 HID0 register, needed for little-endian mode support. As a consequence, we need to merge hflags coming from MSR with other ones. Use little-endian mode from hflags instead of MSR during code translation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3524 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-03PowerPC MMU and exception fixes:j_mayer
* PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than later PowerPC implementation. * Bugfix in BATs check: must not stop after 4 BATs when more are provided. * Enable POWER 'rac' instruction. * Fix exception prefix for all supported PowerPC implementations. * Fix exceptions, MMU model and bus model for PowerPC 601 & 620. * Enable PowerPC 620 as it could mostly boot a PreP target. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3518 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29Fix two PowerPC FPU emulation bugs (thanks to Aurelien Jarno)j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3487 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28Make Alpha and PowerPC targets use shared helpersj_mayer
for clz, clo, ctz, cto and ctpop. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3466 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28PowerPC coding style and inlining fixes.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27PowerPC floating-point helper typo.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3460 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27PowerPC float bugfix: 64 bits float mantissa is 52 bits long.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3459 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-27Fix PowerPC FPSCR update and floating-point exception generationj_mayer
in most useful cases. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25Fix PowerPC 64x64 bits multiplication overflow check.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3444 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25Use host-utils for PowerPC 64 64x64 bits multiplications.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3442 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-25Gprof prooved the PowerPC emulation spent too much time in MSR load and storej_mayer
routines. Coming back to a raw MSR storage model then speed-up the emulation. Improve fast MSR updates (wrtee wrteei and mtriee cases). Share rfi family instructions helpers code to avoid bug in duplicated code. Allow entering halt mode as the result of a rfi instruction. Add a new helper_regs.h file to avoid duplication of special registers manipulation routines (currently XER and MSR). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3436 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Generate micro-ops for PowerPC hypervisor mode.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3386 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-07PowerPC target optimisations: make intensive use of always_inline.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3347 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-04Make PowerPC cache line size implementation dependant.j_mayer
Implement dcbz tunable cache line size for PowerPC 970. Make hardware reset vector implementation dependant. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-01Handle all MMU models in switches, even if it's just to abort because of lackj_mayer
of supporting code. Implement 74xx software TLB model. Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss on those processors. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-01Avoid op helpers that would just call helpers for TLB & SLB management:j_mayer
call the helpers directly from the micro-ops. Avoid duplicated code for tlbsx. implementation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3302 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30* Update OEA environment, following the PowerPC 2.04 specification:j_mayer
- New mtmsr/mtmsrd form that just update RI and EE bits - New hrfid, lq and stq instructions - Add support for supervisor and hypervisor modes process priority update - Code provision for hypervisor SPR accesses * Actually implement the wait instruction * Bugfixes (missing RETURN in micro-op / missing #ifdef) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3289 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30Implement Process Priority Register as defined in the PowerPC 2.04 spec.j_mayer
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3282 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-03 18:26:06 +0000