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path: root/target-ppc/op.c
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2008-12-07target-ppc: convert SPR accesses to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06target-ppc: convert SLB/TLB instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06target-ppc: convert dcr load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06target-ppc: convert msr load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06target-ppc: convert POWER bridge instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-05target-ppc: convert POWER shift instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5882 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert PPC 440 instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert return from interrupt instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert external load/store instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5831 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert dcbz instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert wait instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5824 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert mfrom instruction to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5823 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: remove dead code from op.caurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5822 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30target-ppc: convert software TLB instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5819 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-27target-ppc: convert SPE load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-24target-ppc: convert trap instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-23target-ppc: convert SPE FP ops to TCGaurel32
Including a few bug fixes: - Don't clear high part for instruction with 32-bit destination - Fix efscmp* and etstcmp* return value Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5783 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22target-ppc: convert exceptions generation to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19target-ppc: convert fp ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-10target-ppc: convert most SPE integer instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01target-ppc: convert 405 MAC instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5591 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-01target-ppc: convert arithmetic functions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-27target-ppc: convert rotation instructions to TCGaurel32
Also fix rlwimi and rldimi for corner cases. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5555 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: convert branch related instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5508 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: convert logical instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: convert crf related instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-ppc: Convert XER accesses to TCGaurel32
Define XER bits as a single register and access them individually to avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit registers). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-15PPC: convert SPE logical instructions to TCGaurel32
(Nathan Froyd) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-14PPC: convert effective address computation to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01target-ppc: fix computation of XER.{CA, OV} in addme, subfmeaurel32
(Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5380 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01target-ppc: fix mullw/mullwoaurel32
Based on patch by Julian Seward. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5379 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14ppc: Convert op_andi to TCGaurel32
Replace op_andi_... with tcg_gen_andi_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5218 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14ppc: Convert ctr, lr moves to TCGaurel32
Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr} with tcg_gen_mov_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05ppc: Convert op_subf to TCGaurel32
Replace op_subf with tcg_gen_sub_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05ppc: Convert op_add, op_addi to TCGaurel32
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: replace op_set_FT0 with tcg_gen_movi_i64aurel32
Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert nip moves to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert CRF moves to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert FPR moves to TCGaurel32
Replace op_{load,store}_fpr with tcg_gen_mov_i64. Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2]. This obsoletes op_template.h for REG > 7. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02[ppc] Convert op_moven_T2_T0 to TCGaurel32
Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02[ppc] Convert op_reset_T0, op_set_{T0, T1} to TCGaurel32
Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02[ppc] Convert op_move_{T1,T2}_T0 to TCGaurel32
Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with tcg_gen_mov_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24Revert commits 5082 and 5083aurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5084 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-24PPC: Switch a few instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07Revert revisions r4168 and r4169. That's work in progress, not ready for ↵aurel32
trunk yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-07Always enable precise emulation when softfloat is usedaurel32
The patch below changes the way to enable softfloat on the PPC target. It is now enabled when softfloat is used. The rationale behind this change is that persons who want precise emulation prefer precision over emulation speed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13Use float32/64 instead of float/doubleaurel32
The patch below uses the float32 and float64 types instead of the float and double types in the PPC code. This doesn't change anything when using softfloat-native as the types are the same, but that helps compiling the PPC target with softfloat. It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and use them instead of identical unions that are defined in numerous places. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01use the TCG code generatorbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-16Always make PowerPC hypervisor mode memory accesses and instructionsj_mayer
available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator. Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3654 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-12Allow use of SPE extension by all PowerPC targets,j_mayer
adding gprh registers to store GPR MSBs when GPRs are 32 bits. Remove not-needed-anymore ppcemb-linux-user target. Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-04 07:28:34 +0000