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path: root/target-ppc/helper_regs.h
AgeCommit message (Expand)Author
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt
2014-04-08PPC: Only enter MSR_POW when no interrupts pendingAlexander Graf
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber
2013-12-20PPC: Add VSX to hflagsAlexander Graf
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber
2009-08-16Replace always_inline with inlineBlue Swirl
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
2008-10-21target-ppc: Convert XER accesses to TCGaurel32
2008-09-04ppc: cleanup register typesaurel32
2007-11-17PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.j_mayer
2007-11-17Always make all PowerPC exception definitions visible.j_mayer
2007-11-04PowerPC 601 need specific callbacks for its BATs setup.j_mayer
2007-10-25Implement power-management for all defined PowerPC CPUs.j_mayer
2007-10-25Gprof prooved the PowerPC emulation spent too much time in MSR load and storej_mayer
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