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path: root/target-ppc/helper.h
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2015-01-07target-ppc: Introduce tbeginTom Musta
Provide a degenerate implementation of the tbegin instruction. This implementation always fails the transaction, recording the failure per Book II Section 5.3.2 of the Power ISA V2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta
The set_fprf argument to the helper_compute_fprf helper function is no longer necessary -- the helper is only invoked when FPSCR[FPRF] is going to be set. Eliminate the unnecessary argument from the function signature and its corresponding implementation. Change the return value of the helper to "void". Update the name of the local variable "ret" to "fprf", which now makes more sense. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard
This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Implement mulldo with TCGTom Musta
Optimize mulldo by using the muls2_i64 operation rather than a helper. Eliminate the obsolete helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy
This adds TM (Transactional Memory) SPRs. This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to handle upper half SPRs such as TEXASRU which is upper half of TEXASR. Since this is not the only register like that and their numbers go consequently, it makes sense to generalize the helpers. This adds a gen_msr_facility_check() helper which purpose is to generate the Facility Unavailable exception if the facility is disabled. It is a copy of gen_fscr_facility_check() but it checks for enabled facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause in FSCR/HFSCR (whichever is passed to the helper). This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32 which are used for TM SPRs. This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class' msr_mask. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy
This adds an FSCR (Facility Status and Control Register) SPR. This defines names for FSCR bits. This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU). This registers an interrupt vector for it at 0xF60 as PowerISA defines. This adds a TCG helper_fscr_facility_check() helper to raise an exception if the facility is not enabled. It updates the interrupt cause field in FSCR. This adds a TCG translation block generation code. The helper may be used for HFSCR too as it has the same format. The helper raising FU exceptions is not used by this patch but will be in the next ones. This adds gen_update_current_nip() to update NIP in DisasContext. This helper is not used now and will be called before checking for a condition for throwing an FU exception. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Fix MMUCSR0 emulationAlex Zuepke
A "mtspr SPRMMUCSR0, reg" always flushed TLB0, because it passed the SPR number 0x3f4 to the flush routine. But we want to flush either TLB0 or TBL1 depending on the GPR value. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> [agraf: change subject line, fix TCGv size mismatch] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Shift SignificandTom Musta
Add emulation of the PowerPC Decimal Floating Point Shift Significand Left Immediate (dscli[q][.]) and DFP Shift Significant Right Immediate (dscri[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Insert Biased ExponentTom Musta
Add emulation of the PowerPC Decimal Floating Point Insert Biased Exponent instructions diex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Extract Biased ExponentTom Musta
Add emulation of the PowerPC Decimal Floating Point Extract Biased Exponent instructions dxex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Encode BCD to DPDTom Musta
Add emulation of the PowerPC Decimal Floating Point Encode Binary Coded Decimal to Densely Packed Decimal instructions denbcd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Decode DPD to BCDTom Musta
Add emulation of the Power PC Decimal Floating Point Decode Densely Packed Decimal to Binary Coded Decimal instructions ddedpd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to FixedTom Musta
Add emulation of the PowerPC Decimal Floating Point Convert to Fixed instructions dctfix[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to FixedTom Musta
Add emulation of the PowerPC Decimal Floating Point Convert to Fixed instructions dctfix[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce Round to DFP Short/LongTom Musta
Add emulation of the PowerPC Round to DFP Short (drsp[.]) and Round to DFP Long (drdpq[.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to Long/ExtendedTom Musta
Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and Convert to DFP Extended (dctqpq[.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Round to IntegerTom Musta
Add emulation of the PowerPC Decimal Floating Point (DFP) Round to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP Integer Without Inexact (drintn[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP ReroundTom Musta
Add emulation of the PowerPC Decimal Floating Point Reround instructions drrnd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP QuantizeTom Musta
Add emulation of the PowerPC Decimal Floating Point Quantize instructions dquai[q][.] and dqua[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test SignificanceTom Musta
Add emulation of the PowerPC Decimal Floating Point Test Significance instructions dtstsf[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test ExponentTom Musta
Add emulation of the PowerPC Decimal Floating Point Test Exponent instructions dtstex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test Data GroupTom Musta
Add emulation of the PowerPC Decimal Floating Point Test Data Group instructions dtstdg[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test Data ClassTom Musta
Add emulation of the PowerPC Decimal Floating Point Test Data Class instructions dtstdc[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP ComparesTom Musta
Add emulation of the PowerPC Decimal Floating Point Compare instructions dcmpu[q] and dcmpo[q]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP DivideTom Musta
Add emulation of the PowerPC Decimal Floating Point Divide instructions ddiv[q][.] Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP MultiplyTom Musta
Add emulation of the PowerPC Decimal Floating Point Multiply instructions dmul[q][.] Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP SubtractTom Musta
Add emulation of the PowerPC Decimal Floating Point Subtract instructions dsub[q][.] Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP AddTom Musta
Add emulation of the PowerPC Decimal Floating Point Add instructions dadd[q][.] Various GCC unused annotations are removed since it is now safe to remove them. Signed-off-by: Tom Musta <tommusta@gmail.com> [agraf: move brace in function definition] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Define FPR Pointer Type for HelpersTom Musta
Define a floating pointer register pointer type in the PowerPC helper header. The type will be used to pass FPR register operands to Decimal Floating Point (DFP) helpers. A pointer is used because the quad word forms of PowerPC DFP instructions operate on adjacent pairs of floating point registers and thus can be thought of as arrays of length 2. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-05target-ppc: Altivec 2.07: Vector Permute and Exclusive ORTom Musta
This patch adds the Vector Permuate and Exclusive OR (vpermxor) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector SHA Sigma InstructionsTom Musta
This patch adds the Vector SHA Sigma instructions introduced in Power ISA Version 2.07: - Vector SHA-512 Sigma Doubleword (vshasigmad) - Vector SHA-256 Sigma Word (vshasigmaw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: AES InstructionsTom Musta
This patch adds the Vector AES instructions introduced in Power ISA Version 2.07: - Vector AES Cipher (vcipher) - Vector AES Cipher Last (vcipherlast) - Vector AES Inverse Cipher (vncipher) - Vector AES Inverse Cipher Last (vncipherlast) - Vector AES SubBytes (vsbox) Note that the implementation of vncipher deviates from the RTL in ISA V2.07. However it does match the verbal description in the third paragraph. The RTL will be fixed in ISA V2.07B. The implementation here has been tested against actual P8 hardware. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Binary Coded Decimal InstructionsTom Musta
This patch add the Binary Coded Decimal instructions bcdadd. and bcdsub. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Polynomial Multiply SumTom Musta
This patch adds the Vectory Polynomial Multiply Sum instructions introduced in Power ISA Version 2.07: - Vectory Polynomial Multiply Sum Byte (vpmsumb) - Vectory Polynomial Multiply Sum Halfword (vpmsumh) - Vectory Polynomial Multiply Sum Word (vpmsumw) - Vectory Polynomial Multiply Sum Doubleword (vpmsumd) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Gather Bits by BytesTom Musta
This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd) instruction which is introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Doubleword ComparesTom Musta
This patch adds the Vector Compare Doubleword instructions introduced by Power ISA Version 2.07: - Vector Compare Equal to Unsigned Doubleword (vcmpequd) - Vector Compare Greater Than Signed Doubleword (vcmpgtsd) - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud) These instructions are encoded with bit 31 set to 1 and so are duals with vcmpeqfp, vcmpgtfp and vcmpbfp respectively. The helper macro for integer compares is enhanced to account for 64-bit operands. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vbpermq InstructionTom Musta
This patch adds the Vector Bit Permute Quadword (vbpermq) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Quadword Addition and SubtracationTom Musta
This patch adds the Vector Quadword Addition and Subtraction instructions introduced in Power ISA Version 2.07: - Vector Add Unsigned Quadword Modulo (vadduqm) - Vector Add & Write Carry Unsigned Quadword (vaddcuq) - Vector Add Extended Unsigned Quadword (vaddeuqm) - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq) - Vector Subtract Unsigned Quadword Modulo (vsubuqm) - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq) - Vector Subtract Extended Unsigned Quadword (vsubeuqm) - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift InstructionsTom Musta
This patch adds the vector doublword rotate and shift instructions introduced in Power ISA Version 2.07: - Vector Rotate Left Doubleword instruction (vrld) - Vector Shift Left Doubleword (vsld) - Vector Shift Right Doubleword (vsrd) - Vector Shift Right Algegbraic Doubleword (vsrad) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta
This patch adds the Unpack Signed Word instructions introduced in Power ISA Version 2.07: - Vector Unpack High Signed Word (vupkusw) - Vector Unpack Low Signed Word (vupklsw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta
This patch adds the Vector Pack Doubleword instructions introduced in Power ISA Version 2.07: - Vector Pack Signed Doubleword Signed Saturate (vpksdss) - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus) - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum) - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta
This patch adds the Vector Minimum and Maximum Doubleword instructions that are introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta
This patch adds the Vector Population Count instructions introduced in Power ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta
This patch adds the Vector Count Leading Zeroes instructions introduced in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vmuluw InstructionTom Musta
This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm) instruction. The existing VARITH_DO macro is re-used to (trivially) instantiate the helper code. Since bits 21-31 of any vmuluwm instruction is 137, the instruction is coded as a dual to vmulouw (bits 21-31 = 136). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta
This patch adds the Multilpy Even/Odd Word instructions that are introduced in Power ISA Version 2.07: - Vector Multiply Even Unsigned Word (vmuleuw) - Vector Multiply Even Signed Word (vmulesw) - Vector Multiply Odd Unsigned Word (vmulouw) - Vector Multiply Odd Signed Word (vmulosw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword ModuloTom Musta
This patch adds two Altivec unsigned doublword modulo instructions that are introduced in Power ISA Version V2.07: - vaddudm : Vector Add Unsigned Doubleword Modulo - vsubudm : Vector Subtrace Unsigned Doubleword Modulo Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 ftsqrtTom Musta
This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 ftdiv InstructionTom Musta
This patch adds the Floating Point Test for Divide instruction which was introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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