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path: root/target-ppc/cpu.h
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2012-12-19exec: move include files to include/exec/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-14target-ppc: Don't use hwaddr to represent hardware stateDavid Gibson
The hwaddr type is somewhat vaguely defined as being able to contain bus addresses on the widest possible bus in the system. For that reason it's discouraged for representing specific pieces of persistent hardware state, which should instead use an explicit width type that matches the bits available in real hardware. In particular, because of the possibility that the size of hwaddr might change if different buses are added to the target in future, it's not suitable for use in vm state descriptions for savevm and migration. This patch purges such unwise uses of hwaddr from the ppc target code, which turns out to be just one. The ppcemb_tlb_t struct, used on a number of embedded ppc models to represent a TLB entry contains a hwaddr for the real address field. This patch changes it to be a fixed uint64_t which is suitable enough for all machine types which use this structure. Other uses of hwaddr in CPUPPCState turn out not to be problematic: htab_base and htab_mask are just used for the convenience of the TCG code; the underlying machine state is the SDR1 register, which is stored with a suitable type already. Likewise the mpic_cpu_base field is only used internally and does not represent fundamental hardware state which needs to be saved. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-03Merge branch 'trivial-patches' of git://github.com/stefanha/qemuBlue Swirl
* 'trivial-patches' of git://github.com/stefanha/qemu: pc: Drop redundant test for ROM memory region exec: make some functions static target-ppc: make some functions static ppc: add missing static vnc: add missing static vl.c: add missing static target-sparc: make do_unaligned_access static m68k: Return semihosting errno values correctly cadence_uart: More debug information Conflicts: target-m68k/m68k-semi.c
2012-11-01target-ppc: make some functions staticBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-11-01ppc: add missing staticBlue Swirl
Add missing 'static' qualifiers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori
* afaerber/qom-cpu: (35 commits) target-i386: Pass X86CPU to kvm_handle_halt() target-i386: Pass X86CPU to kvm_get_mp_state() cpu: Move thread_id to CPUState cpus: Pass CPUState to run_on_cpu() target-i386: Pass X86CPU to cpu_x86_inject_mce() target-i386: Pass X86CPU to kvm_mce_inject() cpus: Pass CPUState to [qemu_]cpu_has_work() spapr: Pass PowerPCCPU to hypercalls spapr: Pass PowerPCCPU to spapr_hypercall() target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall target-ppc: Pass PowerPCCPU to powerpc_excp() xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb() cpus: Pass CPUState to qemu_wait_io_event_common() cpus: Pass CPUState to flush_queued_work() cpu: Move queued_work_{first,last} to CPUState cpus: Pass CPUState to qemu_cpu_kick() target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU ppc: Pass PowerPCCPU to {ppc6xx,ppc970,power7,ppc40x,ppce500}_set_irq() cpus: Pass CPUState to qemu_tcg_init_vcpu() cpus: Pass CPUState to qemu_tcg_cpu_thread_fn ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01target-ppc: Extend FPU state for newer POWER CPUsDavid Gibson
This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr is extended to a target_ulong bits, since some recent (64 bit) CPUs now have more status bits than fit inside 32 bits. Also, we add the 32 VSR registers present on CPUs with VSX (these extend the standard FP regs, which together with the Altivec/VMX registers form a 64 x 128bit register file for VSX). We don't actually support the instructions using these extra registers in TCG yet, but we still need a place to store the state so we can sync it with KVM and savevm/loadvm it. This patch updates the savevm code to not fail on the extended state, but also does not actually save it - that's a project for another patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01target-ppc: Rework storage of VPA registration stateDavid Gibson
We change the storage of the VPA information to explicitly use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix commit message] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-31target-ppc: Pass PowerPCCPU to cpu_ppc_hypercallAndreas Färber
Adapt emulate_spapr_hypercall() accordingly. Needed for changing spapr_hypercall() argument type to PowerPCCPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-10-29target-ppc: Rework storage of VPA registration stateDavid Gibson
With PAPR guests, hypercalls allow registration of the Virtual Processor Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow for certain communication between the guest and hypervisor. Currently, we store the addresses of the three areas and the size of the dtl in CPUPPCState. The SLB shadow and DTL are variable sized, with the size being retrieved from within the registered memory area at the hypercall time. This size can later be overwritten with other information, however, so we need to save the size as of registration time. We already do this for the DTL, but not for the SLB shadow, so this patch fixes that. In addition, we change the storage of the VPA information to use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-04target-ppc: Remove unused power_mode field from cpu stateDavid Gibson
CPUPPCState includes a variable 'power_mode' which is used nowhere. This patch removes it. This includes saving a dummy zero in its place during vmsave, to avoid breaking the save format. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE206: Bump MAS2 to 64bitAlexander Graf
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page address. So increase the mask for its EPN. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Implement EPR SPRAlexander Graf
On the e500 series, accessing SPR_EPR magically turns into an access at that CPU's IACK register on the MPIC. Implement that logic to get kernels that make use of that feature work. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add support for MSR_CMAlexander Graf
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to support running 64bit code with MSR_CM set. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add some booke SPR definesAlexander Graf
The number of SPRs avaiable in different PowerPC chip is still increasing. Add definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc64: Rudimentary Support for extra page sizes on server CPUsBenjamin Herrenschmidt
More recent Power server chips (i.e. based on the 64 bit hash MMU) support more than just the traditional 4k and 16M page sizes. This can get quite complicated, because which page sizes are supported, which combinations are supported within an MMU segment and how these page sizes are encoded both in the SLB entry and the hash PTE can vary depending on the CPU model (they are not specified by the architecture). In addition the firmware or hypervisor may not permit use of certain page sizes, for various reasons. Whether various page sizes are supported on KVM, for example, depends on whether the PR or HV variant of KVM is in use, and on the page size of the memory backing the guest's RAM. This patch adds information to the CPUState and cpu defs to describe the supported page sizes and encodings. Since TCG does not yet support any extended page sizes, we just set this to NULL in the static CPU definitions, expanding this to the default 4k and 16M page sizes when we initialize the cpu state. When using KVM, however, we instead determine available page sizes using the new KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use some defaults, with some guesswork which should do the right thing for existing HV and PR implementations. The fallback might not be correct for future versions, but that's ok, because they'll have KVM_PPC_GET_SMMU_INFO. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Cleanup MMU mergeBlue Swirl
Remove useless wrappers. In some cases 'int' parameters are changed to uint32_t. Make internal functions static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> [agraf: fix kvm compilation] Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Move exception helpers from helper.c to excp_helper.cBlue Swirl
Move exception helpers from helper.c to excp_helper.c and make cpu_dump_rfi() static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-04target-ppc: Let cpu_ppc_init() return PowerPCCPUAndreas Färber
Adapt e500 mpc8544ds machine accordingly. Turn cpu_init() into a static inline function returning CPUPPCState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Alexander Graf <agraf@suse.de>
2012-04-15target-ppc: QOM'ify CPUAndreas Färber
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Drop cpu_ppc_close()Andreas Färber
It is unused, so avoid QOM'ifying it unneededly. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-07Replace Qemu by QEMU in commentsStefan Weil
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-15PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth
These instructions for loading and storing byte-swapped 64-bit values have been introduced in PowerISA 2.06. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-ppc: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14PPC: 405: Use proper CPU resetAlexander Graf
On ppc405ep there is a register that allows for software to reset the core, but not the whole system. Implement this reset using a reset interrupt. This gets rid of a bunch of #if 0'ed code. Reported-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-02-02PPC: Add CPU feature for processor controlAlexander Graf
We're soon going to implement processor control features. Add the feature flag, so we're well prepared. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Add doorbell definesAlexander Graf
We're going to introduce doorbell instructions (called processor control in the spec) soon. Add some defines for easier patch readability later. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Add some more excp vectorsAlexander Graf
Our EXCP list is getting outdated. By now, 3 new exception vectors have been introduced. Update the list so we have everything at one place. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Check for TLB overrunAlexander Graf
Our internal helpers to fetch TLB entries were not able to tell us that an entry doesn't even exist. Pass an error out if we hit such a case to not accidently pass beyond the TLB array. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke: add tlbnps handlingAlexander Graf
When using MAV 2.0 TLB registers, we have another range of TLB registers available to read the supported page sizes from. Add SPR definitions for those and add a helper function that we can use to receive such a bitmap even when using MAV 1.0. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: Add IVOR 38-42Alexander Graf
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <afaerber@suse.de>
2011-12-02fix spelling in target sub directoryDong Xu Wang
Cc: Richard Henderson <rth@twiddle.net> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-31ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson
The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them. However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Correct vmx/dfp handling in both KVM and TCG casesDavid Gibson
Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30PPC: Bump qemu-system-ppc to 64-bit physical address spaceAlexander Graf
Some 32-bit PPC CPUs can use up to 36 bit of physical address space. Treat them accordingly in the qemu-system-ppc binary type. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: First cut implementation of -cpu hostDavid Gibson
For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: booke timersFabien Chouteau
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pagesScott Wood
This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: add "info tlb" supportScott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06kvm: ppc: booke206: use MMU APIScott Wood
Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-08-23PPC: E500: Add ESR bit definitionsAlexander Graf
The BookE spec specifies a number of ESR bits. Add defines for them so we can use them later on. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-12target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell
Remove the include of setjmp.h from the cpu.h of target-alpha and target-ppc. This is unnecessary because cpu-defs.h already includes this header; this change brings these two targets into line with all the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-17PPC: move TLBs to their own arraysAlexander Graf
Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
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