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path: root/target-ppc/cpu.h
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2015-04-28Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi
This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost
Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-03-09PPC: Introduce the Virtual Time Base (VTB) SPR registerCyril Bur
This patch adds basic support for the VTB. PowerISA: The Virtual Time Base (VTB) is a 64-bit incrementing counter. Virtual Time Base increments at the same rate as the Time Base until its value becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when this occurs. The operation of the Virtual Time Base has the following additional properties. 1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of the Virtual Time Base. 2. Copying the contents of a GPR to the Virtual Time Base replaces the contents of the Virtual Time Base with the contents of the GPR. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-03-09target-ppc: Use right page size with hash table lookupAneesh Kumar K.V
We look at two sizes specified in ISA (4K, 64K). If not found matching, we consider it 16MB. Without this patch we would fail to lookup address above 16MB range. Below 16MB happened to work before because the kernel have a liner mapping and we always looked up hash for 0xc000000000000000. The actual real address was computed by using the 16MB offset with the real address found with the above hash. Without Fix: (gdb) x/16x 0xc000000001000000 0xc000000001000000 <list_entries+453208>: Cannot access memory at address 0xc000000001000000 (gdb) With Fix: (gdb) x/16x 0xc000000001000000 0xc000000001000000 <list_entries+453208>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000010 <list_entries+453224>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000020 <list_entries+453240>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000030 <list_entries+453256>: 0x00000000 0x00000000 0x00000000 0x00000000 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell
The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
2015-01-10Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' ↵Peter Maydell
into staging Patch queue for ppc - 2015-01-07 New year's release. This time's highlights: - E500: More RAM support - pseries: New SLOF release - Migration fixes - Simplify USB spawning logic, removes support for explicit usb=off - TCG: Simple untansactional TM emulation # gpg: Signature made Wed 07 Jan 2015 15:19:37 GMT using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" * remotes/agraf/tags/signed-ppc-for-upstream: (37 commits) hw/ppc/mac_newworld: simplify usb controller creation logic hw/ppc/spapr: simplify usb controller creation logic hw/ppc/mac_newworld: QOMified mac99 machines hw/usb: simplified usb_enabled hw/machine: added machine_usb wrapper hw/ppc: modified the condition for usb controllers to be created for some ppc machines target-ppc: Cast ssize_t to size_t before printing with %zx target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY PPC: e500: Fix GPIO controller interrupt number target-ppc: Introduce Privileged TM Noops target-ppc: Introduce tcheck target-ppc: Introduce TM Noops target-ppc: Introduce tbegin target-ppc: Introduce TEXASRU Bit Fields target-ppc: Power8 Supports Transactional Memory target-ppc: Introduce tm_enabled Bit to CPU State target-ppc: Introduce Feature Flag for Transactional Memory target-ppc: Introduce Instruction Type for Transactional Memory pseries: Update SLOF firmware image to 20141202 PPC: Fix crash on spapr_tce_table_finalize() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-01-07target-ppc: Introduce TEXASRU Bit FieldsTom Musta
Define mnemonics for the various bit fields in the Transaction EXception And Summary Register (TEXASR). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07target-ppc: Introduce Feature Flag for Transactional MemoryTom Musta
Add a flag (POWERPC_FLAG_TM) for the Transactional Memory Facility introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-01-07target-ppc: Introduce Instruction Type for Transactional MemoryTom Musta
Add a category (PPC2_TM) for the Transactional Memory instructions introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-12-23target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-04target-ppc: Use macros in opcodes table handling codeBharata B Rao
Define and use macros instead of direct numbers wherever possible in ppc opcodes table handling code. This doesn't change any code functionality. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard
This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-25target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson
Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-22-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-29target-ppc: enable virtio endian ambivalent supportGreg Kurz
The device endianness is the cpu endianness at device reset time. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-06-27target-ppc: Add DFP to Emulated Instructions FlagTom Musta
Decimal Floating Point is emulated, so add it the mask. This will fix the erroneous message: Warning: Disabling some instructions which are not emulated by TCG (0x0, 0x4) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from the H_SET_MODE, for POWER8 (PowerISA 2.07) only. This defines AIL flags for LPCR special register. This changes @excp_prefix according to the mode, takes effect in TCG. This turns support of a new capability PPC2_ISA207S flag for TCG. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's Event Based Branch (EBB) control SPRsAlexey Kardashevskiy
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via set of SPRs access to which should generate an "Facility Unavailable" interrupt if the facilities are not enabled in FSCR for problem state. This adds EBB SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16KVM: target-ppc: Enable TM state migrationAlexey Kardashevskiy
This adds migration support for registers saved before Transactional Memory (TM) transaction started. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy
This adds TM (Transactional Memory) SPRs. This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to handle upper half SPRs such as TEXASRU which is upper half of TEXASR. Since this is not the only register like that and their numbers go consequently, it makes sense to generalize the helpers. This adds a gen_msr_facility_check() helper which purpose is to generate the Facility Unavailable exception if the facility is disabled. It is a copy of gen_fscr_facility_check() but it checks for enabled facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause in FSCR/HFSCR (whichever is passed to the helper). This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32 which are used for TM SPRs. This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class' msr_mask. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's MMCR2/MMCRS SPRsAlexey Kardashevskiy
This adds POWER8 specific PMU MMCR2/MMCRS SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy
This adds an FSCR (Facility Status and Control Register) SPR. This defines names for FSCR bits. This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU). This registers an interrupt vector for it at 0xF60 as PowerISA defines. This adds a TCG helper_fscr_facility_check() helper to raise an exception if the facility is not enabled. It updates the interrupt cause field in FSCR. This adds a TCG translation block generation code. The helper may be used for HFSCR too as it has the same format. The helper raising FU exceptions is not used by this patch but will be in the next ones. This adds gen_update_current_nip() to update NIP in DisasContext. This helper is not used now and will be called before checking for a condition for throwing an FU exception. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's TIR SPRAlexey Kardashevskiy
This adds TIR (Thread Identification Register) SPR first defined for server CPUs in PowerISA 2.07. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add HID4 SPR for PPC970Alexey Kardashevskiy
Previously LPCR was registered for the 970 class which was wrong as it does not have LPCR. Instead, HID4 is used which this patch registers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add PMC7/8 to 970 classAlexey Kardashevskiy
Compared to PowerISA-compliant CPUs, 970 family has most of them plus PMC7/8 which are only present on 970 but not on POWER5 and later CPUs. Since we are changing SPRs for Book3s/970 families, let's add them too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add "POWER" prefix to MMCRA PMU registersAlexey Kardashevskiy
Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish the transition and fix MMCRA and define a supermode version of it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Copy and split gen_spr_7xx() for 970Alexey Kardashevskiy
This stops using 7xx common SPRs init function and adds separate set of helpers for 970. This does not copy ICTC SPR as neither 970 manual nor PowerISA mention it. This defines 970/book3s PMU SPRs constants as they differs from the ones used for 7XX. This creates 2 helpers for PMU SPRs, one for supermode privileged SPRs and one for user privileged SPRs as "sup" versions can be shared across the family while "user" versions will behave different starting POWER8 (which will be addressed later). This allows writing to Uxxxx SPRs from supermode. spr_write_ureg() is implemented for this as a copy of already existing spr_read_ureg(). This allows writing to supervisor's SIAR - it used to be disabled when gen_spr_7xx() was used. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Merge 970FX and 970MP into a single 970 classAlexey Kardashevskiy
The differences between classes were: 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all; 2. check_pow() callback, HID0 format is the same so should be the same 0x01C00000 which means "deep nap", "doze" and "nap" bits set; 3. LPCR - 970 does not have it but 970MP had one (by mistake). This fixes wrong differences and makes one 970 class. This fixes wrong registration of LPCR which is not present on 970. This defines HID0 bits and uses them in check_pow_970(). This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to 970 class as we do not emulate hypervisor in QEMU anyway. This does not remove check_pow_970FX now as it is still used by POWER5+ class, this will be addressed later. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRsAlexey Kardashevskiy
As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers for 32 and 64 bit POWERPC. We are going to support 64bit versions too so let's rename 32bit ones to avoid confusion. This is a mechanical patch so it does not fix obvious mistake with these registers in POWER7 yet, this will be fixed later. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf
Today we have a lot of conditional code in the SPE emulation depending on whether we have 64bit GPRs or not. Unfortunately the assumption that we can just recycle the 64bit GPR implementation is wrong. Normal SPE implementations maintain the upper 32 bits on all non-SPE instructions which then only modify the low 32 bits. However all instructions we model that adhere to the normal SF based switching don't care whether they operate on 32 or 64 bit registers and just always use the full 64 bits. So let's remove that dubious SPE optimization and revert everything to the same code path the 32bit target code was taking. That way we get rid of differences between the two implementations, but will get a slight performance hit when emulating SPE instructions. This fixes SPE emulation with qemu-system-ppc64 for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy
This puts a limit to the number of threads per core based on the current compatibility mode. Although PowerISA specs do not specify the maximum threads per core number, the linux guest still expects that PowerISA2.05-compatible CPU supports only 2 threads per core as this is what POWER6 (2.05 compliant CPU) implements, the same is for POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads). This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of threads which affects ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. The number of CPU nodesremains unchanged. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy
This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Properly emulate L1CSR0 and L1CSR1Alexander Graf
There are 2 L1 cache control registers - one for data (L1CSR0) and one for instructions (L1CSR1). Emulate both of them well enough to give the guest the illusion that it could actually do anything about its caches. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add L1CFG1 SPR emulationAlexander Graf
In addition to the L1 data cache configuration register L1CFG0 there is also another one for the L1 instruction cache called L1CFG1. Emulate that one with the same values as the data one. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add definitions for GIVORsAlexander Graf
We're missing SPR definitions for GIVORs. Add them to the list of SPRs. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-13cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-04-08PPC: Clean up DECR implementationAlexander Graf
There are 3 different variants of the decrementor for BookE and BookS. The BookE variant sets TSR[DIS] to 1 when the DEC value becomes 1 or 0. TSR[DIS] is then the indicator whether the decrementor interrupt line is asserted or not. The old BookS variant treats DEC as an edge interrupt that gets triggered when the DEC value's top bit turns 1 from 0. The new BookS variant maintains the assertion bit inside DEC itself. Whenever the DEC value becomes negative (top bit set) the DEC interrupt line is asserted. So far we implemented mostly the old BookS variant. Let's do them all properly. This fixes booting pseries ppc64 guest images in TCG mode for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-20target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy
This flag will be used to decide whether to emulate some bits of H_SET_MODE hypercall because some are POWER8-only. While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already have it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-20target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy
This resets SPR values to defaults on CPU reset. This should help with little-endian guests reboot issues. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber
Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber
Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-05target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy
Normally CPUState::cpu_index is used to pick the right CPU for various operations. However default consecutive numbering does not always work for POWERPC. These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX and used to call KVM VCPU's ioctls. In order to achieve this, kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies cpu_index by the number of threads per core. This approach has disadvantages such as: 1. NUMA configuration stays broken after the fixup; 2. CPU-targeted commands from the QEMU Monitor do not work properly as CPU indexes have been fixed and there is no clear way for the user to know what the new CPU indexes are. This introduces a @cpu_dt_id field in the CPUPPCState struct which is initialized from @cpu_index by default and can be fixed later to meet the device tree requirements. This adds an API to handle @cpu_dt_id. This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id is calculated in ppc_cpu_realize(). This will be used later in machine code. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix htab_mask calculationAneesh Kumar K.V
Correctly update the htab_mask using the return value of KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1 on GET_SREGS for HV. We check for external htab and if found true, we don't need to update sdr1 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ fixed pte group offset computation in ppc_hash64_htab_lookup() that caused TCG to fail, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Update AVR StructureTom Musta
This patch updates the ppc_avr_t data structure to include elements for signed 64-bit integers and (conditionally) unsigned 128 bit integers. These elements will be in instructions models later on in this patch series. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Instruction FlagTom Musta
This patch adds a flag that will be used to tag the Altivec instructions introduced in Power ISA Version 2.07. The flag is added to Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Load Quadword and ReserveTom Musta
This patch adds the Load Quadword and Reserve (lqarx) instruction, which is new in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta
This patch adds a flag to identify the load/store quadword instructions that are introduced with Power ISA 2.07. The flag is added to the Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta
This patch adds support for the Target Address Register (TAR) to the Power8 model. Because supported SPRs are typically identified in an init_proc_*() function and because the Power8 model is currently just using the init_proc_POWER7() function, a new init_proc_POWER8() function is added and plugged into the P8 model. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for bctarTom Musta
This patch adds a flag for the bctar instruction. This instruction is being introduced via Power ISA 2.07. Also, the flag is added to the Power8 machine model since the P8 processor supports this instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta
This patch adds a flag for Floating Point Test instructions that were introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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