Age | Commit message (Expand) | Author |
2014-06-16 | PPC: e500: Merge 32 and 64 bit SPE emulation | Alexander Graf |
2014-06-16 | spapr: Limit threads per core according to current compatibility mode | Alexey Kardashevskiy |
2014-06-16 | target-ppc: Implement "compat" CPU option | Alexey Kardashevskiy |
2014-06-16 | PPC: Properly emulate L1CSR0 and L1CSR1 | Alexander Graf |
2014-06-16 | PPC: Add L1CFG1 SPR emulation | Alexander Graf |
2014-06-16 | PPC: Add definitions for GIVORs | Alexander Graf |
2014-05-13 | cpu: make CPU_INTERRUPT_RESET available on all targets | Paolo Bonzini |
2014-04-08 | PPC: Clean up DECR implementation | Alexander Graf |
2014-03-20 | target-ppc: Introduce powerisa-207-server flag | Alexey Kardashevskiy |
2014-03-20 | target-ppc: Reset SPRs on CPU reset | Alexey Kardashevskiy |
2014-03-13 | exec: Change cpu_abort() argument to CPUState | Andreas Färber |
2014-03-13 | cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook | Andreas Färber |
2014-03-13 | cpu: Turn cpu_has_work() into a CPUClass hook | Andreas Färber |
2014-03-05 | target-ppc: add PowerPCCPU::cpu_dt_id | Alexey Kardashevskiy |
2014-03-05 | target-ppc: Fix htab_mask calculation | Aneesh Kumar K.V |
2014-03-05 | target-ppc: Altivec 2.07: Update AVR Structure | Tom Musta |
2014-03-05 | target-ppc: Altivec 2.07: Add Instruction Flag | Tom Musta |
2014-03-05 | target-ppc: Add Load Quadword and Reserve | Tom Musta |
2014-03-05 | target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions | Tom Musta |
2014-03-05 | target-ppc: Add Target Address SPR (TAR) to Power8 | Tom Musta |
2014-03-05 | target-ppc: Add Flag for bctar | Tom Musta |
2014-03-05 | target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions | Tom Musta |
2014-03-05 | target-ppc: Add Flag for ISA V2.06 Floating Point Conversion | Tom Musta |
2014-03-05 | target-ppc: Add Flag for ISA2.06 Atomic Instructions | Tom Musta |
2014-03-05 | target-ppc: Add Flag for ISA2.06 Divide Extended Instructions | Tom Musta |
2014-03-05 | target-ppc: Add ISA2.06 bpermd Instruction | Tom Musta |
2014-03-05 | target-ppc: VSX Stage 4: Add VSX 2.07 Flag | Tom Musta |
2014-03-05 | target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers | Alexey Kardashevskiy |
2014-03-05 | target-ppc: fix LPCR SPR number | Alexey Kardashevskiy |
2013-12-20 | Add MSR VSX and Associated Exception | Tom Musta |
2013-12-20 | Declare and Enable VSX | Tom Musta |
2013-10-25 | target-ppc: Use #define for max slb entries | Aneesh Kumar K.V |
2013-09-02 | target-ppc: USE LPCR_ILE to control exception endian on POWER7 | Anton Blanchard |
2013-07-29 | target-ppc: Convert ppc cpu savevm to VMStateDescription | Alexey Kardashevskiy |
2013-07-23 | cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() | Andreas Färber |
2013-07-09 | linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user | Peter Maydell |
2013-07-01 | target-ppc: Introduce unrealizefn for PowerPCCPU | Andreas Färber |
2013-05-06 | PPC: Add MMU type for 2.06 with AMR but no TB pages | Alexander Graf |
2013-04-26 | target-ppc: add instruction flags for Book I 2.05 | Aurelien Jarno |
2013-04-26 | target-ppc: Add more stubs for POWER7 PMU registers | David Gibson |
2013-04-26 | PPC: Remove env->hreset_excp_prefix | Fabien Chouteau |
2013-03-22 | target-ppc: Move ppc tlb_fill implementation into mmu_helper.c | David Gibson |
2013-03-22 | target-ppc: Split user only code out of mmu_helper.c | David Gibson |
2013-03-22 | mmu-hash64: Implement Virtual Page Class Key Protection | David Gibson |
2013-03-22 | mmu-hash*: Add header file for definitions | David Gibson |
2013-03-22 | target-ppc: mmu_ctx_t should not be a global type | David Gibson |
2013-03-22 | target-ppc: Disentangle BAT code for 32-bit hash MMUs | David Gibson |
2013-03-22 | target-ppc: Don't share get_pteg_offset() between 32 and 64-bit | David Gibson |
2013-03-22 | target-ppc: Disentangle hash mmu helper functions | David Gibson |
2013-03-22 | target-ppc: Disentangle get_physical_address() paths | David Gibson |