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AgeCommit message (Expand)Author
2015-01-20target-mips: Don't use _raw load/store accessorsPeter Maydell
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell
2015-01-12kvm: extend kvm_irqchip_add_msi_route to work on s390Frank Blaschka
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini
2014-12-17Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into stagingPeter Maydell
2014-12-16qemu-log: add log category for MMU infoAntony Pavlov
2014-12-16target-mips: remove excp_names[] from linux-user as it is unusedLeon Alrae
2014-12-16target-mips: convert single case switch into if statementLeon Alrae
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki
2014-12-16target-mips: Use local float status pointer across MSA macrosMaciej W. Rozycki
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki
2014-12-16target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki
2014-12-16target-mips: gdbstub: Clean up FPU register handlingMaciej W. Rozycki
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki
2014-12-16target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki
2014-12-16target-mips: Restore the order of helpersMaciej W. Rozycki
2014-12-16target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki
2014-12-16target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki
2014-12-16target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki
2014-12-16target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki
2014-12-16target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki
2014-12-16target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki
2014-12-16target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki
2014-12-16target-mips: Make CP1.FIR read-only here tooMaciej W. Rozycki
2014-12-16target-mips: Correct the handling of register #72 on writesMaciej W. Rozycki
2014-12-15target-mips: kvm: do not use get_clock()Paolo Bonzini
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki
2014-11-07target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae
2014-11-07mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bitsMaciej W. Rozycki
2014-11-07mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki
2014-11-07mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki
2014-11-03target-mips: add MSA support to mips32r5-genericYongbok Kim
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim
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