| Age | Commit message (Expand) | Author |
|---|
| 2007-04-16 | Simplify branch likely handling. | ths |
| 2007-04-15 | Don't use T2 for INS, it conflicts with branch delay slot handling. | ths |
| 2007-04-15 | Fix qemu SIGFPE caused by division-by-zero due to underflow. | ths |
| 2007-04-15 | Small code generation optimization. | ths |
| 2007-04-15 | Delete unused define. | ths |
| 2007-04-14 | Restart interrupts after an exception. | ths |
| 2007-04-13 | Nicer Log formatting. | ths |
| 2007-04-13 | Another fix for CP0 Cause register handling. | ths |
| 2007-04-11 | Make SYNCI_Step and CCRes CPU-specific. | ths |
| 2007-04-11 | Throw RI for invalid MFMC0-class instructions. Introduce optional | ths |
| 2007-04-11 | Code formatting fix. | ths |
| 2007-04-11 | More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may | ths |
| 2007-04-09 | Fix CP0_IntCtl handling. | ths |
| 2007-04-09 | Proper handling of reserved bits in the context register. | ths |
| 2007-04-09 | Mark watchpoint features as unimplemented. | ths |
| 2007-04-09 | Catch unaligned sc/scd. | ths |
| 2007-04-09 | Fix exception handling cornercase for rdhwr. | ths |
| 2007-04-09 | Remove bogus mtc0 handling. | ths |
| 2007-04-07 | Unify IRQ handling. | pbrook |
| 2007-04-07 | cpu_get_phys_page_debug should return target_phys_addr_t | j_mayer |
| 2007-04-07 | Implement prefx. | ths |
| 2007-04-07 | Set proper BadVAddress value for unaligned instruction fetch. | ths |
| 2007-04-07 | Actually skip over delay slot for a non-taken branch likely. | ths |
| 2007-04-07 | Fix ins/ext cornercase. | ths |
| 2007-04-06 | Fix handling of ADES exceptions. | ths |
| 2007-04-06 | Save state for all CP0 instructions, they may throw a CPU exception. | ths |
| 2007-04-05 | fix branch delay slot cornercases. | ths |
| 2007-04-05 | Fix rotr immediate ops, mask shift/rotate arguments to their allowed | ths |
| 2007-04-05 | Handle EBase properly. | ths |
| 2007-04-05 | Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise | ths |
| 2007-04-05 | 64bit MIPS FPUs have 32 registers. | ths |
| 2007-04-04 | Fix code formatting. | ths |
| 2007-04-02 | MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers | ths |
| 2007-04-02 | Build fix for 64bit machines. (This is still not correct mul/div handling.) | ths |
| 2007-04-01 | Actually enable 64bit configuration. | ths |
| 2007-04-01 | MIPS64 configurations. | ths |
| 2007-03-31 | Malta CBUS UART support. | ths |
| 2007-03-30 | Update mips TODO. | ths |
| 2007-03-30 | Fix typo, suggested by Ben Taylor. | ths |
| 2007-03-30 | Squash logic bugs while they are fresh... | ths |
| 2007-03-30 | Sanitize mips exception handling. | ths |
| 2007-03-24 | One more bit of mips CPU configuration, and support for early 4KEc | ths |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths |
| 2007-03-21 | Move mips CPU specific initialization to translate_init.c. | ths |
| 2007-03-19 | Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil. | ths |
| 2007-03-19 | Define gen_intermediate_code_internal as "static inline". | ths |
| 2007-03-19 | SPARC host fixes, by Ben Taylor. | ths |
| 2007-03-18 | Fix BD flag handling, cause register contents, implement some more bits | ths |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths |
| 2007-03-17 | Note FPU enable/disable issue. | ths |
