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2013-06-28cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber
Use it for all targets, but be careful not to pass invalid CPUState. cpu_single_env can be NULL, e.g. on Xen. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber
This allows to move the call into CPUState's realizefn. Therefore move the stub into libqemustub.a. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-20linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung
The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-20target-mips: clean-up in BIT_INSVPetar Jovanovic
This is a small follow-up change to "fix incorrect behaviour for INSV". It includes two minor modifications: - sizefilter is constant so it can be moved inside of the block, - several lines of the code are replaced with a call to deposit64. No functional change. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-19target-mips: set carry bit correctly in DSPControl registerPetar Jovanovic
First we need to clear the bit and then we set the given value. Instruction ADDSC sets the bit and instruction ADDWC uses this bit. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-19target-mips: fix EXTPDP and setting up pos field in the DSPControl regPetar Jovanovic
This change makes sure that modifications of pos field in the DSPControl register do not trash other bits in the register. This bug can be triggered with the additional test case in mips32-dsp/extpdp.c in this commit. In addition to this, this change corrects incorrect calculation of the mask for EXTPDP. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-17target-mips: fix incorrect behaviour for EXTPPetar Jovanovic
The mask for EXTP instruction when size=31 has not been correctly calculated. The test (mips32-dsp/extp.c) has been extended to include the case that triggers the issue. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-08target-mips: fix incorrect behaviour for INSVPetar Jovanovic
Corner case for INSV instruction when size=32 has not been correctly implemented. The mask for size should be one bit wider, and preparing the filter variable should be aware of this case too. The test for INSV has been extended to include the case that triggers the bug. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-08target-mips: add missing check_dspr2 for multiply instructionsPetar Jovanovic
The emulator needs to check in hflags if DSP unit has been turned off before it generates code for MUL_PH, MUL_S_PH, MULQ_S_W, and MULQ_RS_W. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03target-mips: fix calculation of overflow for SHLL.PH and SHLL.QBPetar Jovanovic
This change corrects and simplifies how discard is calculated for shift left logical vector instructions. It is used to detect overflow and set bit 22 in the DSPControl register. The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases that expose incorrectness in the previous implementation. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-15target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHRPetar Jovanovic
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format. Otherwise, the results are unpredictable. Once the operands were corrected in the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became visible. This change corrects the tests for MAQ_SA_W.PHL/MAQ_SA_W.PHR and fixes sign-related issue in mipsdsp_mul_q15_q15. It also removes unnecessary comment. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
2013-03-17target-mips: fix rndrashift_short_acc and code for EXTR_ instructionsPetar Jovanovic
Fix for rndrashift_short_acc to set correct value to higher 64 bits. This change also corrects conditions when bit 23 of the DSPControl register is set. The existing test files have been extended with several examples that trigger the issues. One bug/example in the test file for EXTR_RS_W has been found and reported by Klaus Peichl. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber
Move it to qom/cpu.h to avoid issues with include order. Change pc_acpi_smi_interrupt() opaque to X86CPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12exec: Pass CPUState to cpu_reset_interrupt()Andreas Färber
Move it to qom/cpu.c to avoid build failures depending on include order of cpu-qom.h and exec/cpu-all.h. Change opaques of various ..._irq_handler() functions to the appropriate CPU type to facilitate using cpu_reset_interrupt(). Fix Coding Style issues while at it (missing braces, indentation). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-05mips64-linux-user: Enable 64-bit address mode and fpuRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05target-mips: Fix accumulator selection for MIPS16 and microMIPSRichard Sandiford
Add accumulator arguments to gen_HILO and gen_muldiv, rather than extracting the accumulator directly from ctx->opcode. The extraction was only right for the standard encoding: MIPS16 doesn't have access to the DSP registers, while microMIPS encodes the accumulator register in a different field (bits 14 and 15). Passing the accumulator register is probably an over-generalisation for division and 64-bit multiplication, which never access anything other than HI and LO, and which always pass 0 as the new argument. Separating them felt a bit fussy though. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-04target-mips: fix DSP overflow macro and affected routinesPetar Jovanovic
The previous implementation incorrectly used same macro to detect overflow for addition and subtraction. This patch makes distinction between these two, and creates separate macros. The affected routines are changed accordingly. This change also includes additions to the existing tests for SUBQ_S_PH and SUBQ_S_W that would trigger the fixed issue, and it removes dead code from the test file. The last test case in subq_s_w.c is a bug found/reported/ isolated by Klaus Peichl from Dolby. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber
Introduce ENV_OFFSET macros which can be used in non-target-specific code that needs to generate TCG instructions which reference CPUState fields given the cpu_env register that TCG targets set up with a pointer to the CPUArchState struct. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-mips: fix for sign-issue in MULQ_W helperPetar Jovanovic
Correct sign-propagation before multiplication in MULQ_W helper. The change also fixes previously incorrect expected values in the tests for MULQ_RS.W and MULQ_S.W. Signed-off-by: Petar Jovanovic <petarj@mips.com> Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: fix for incorrect multiplication with MULQ_S.PHPetar Jovanovic
The change corrects sign-related issue with MULQ_S.PH. It also includes extension to the already existing test which will trigger the issue. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson
Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber
The target-specific ENV_GET_CPU() macros have allowed us to navigate from CPUArchState to CPUState. The reverse direction was not supported. Avoid introducing CPU_GET_ENV() macros by initializing an untyped pointer that is initialized in derived instance_init functions. The field may not be called "env" due to it being poisoned. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber
Make mips_tcg_init() non-static and add tcg_enabled() check to suppress it for qtest. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-mips: Introduce QOM realizefn for MIPSCPUAndreas Färber
Introduce a realizefn and set realized = true from cpu_mips_init(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-31target-mips: enable access to DSP ASE if implementedPetar Jovanovic
compute_hflags() will reset DSP h-flags, so MX bit should be initially set for usermode in cpu_state_reset() if DSP ASE is implemented. This change will bring back user-mode support for DSP ASE, since one of the recent changes broke it. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: Unfuse {,N}M{ADD,SUB}.fmtRichard Sandiford
Turn MADD.fmt, MSUB.fmt, NMADD.fmt and NMSUB.fmt from fused to unfused operations, so that they behave in the same way as a separate multiplication and addition. The instructions were only fused in early MIPS IV processors. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: Sign-extend the result of LWRRichard Sandiford
Sign-extend the result of LWR, as is already done for LWL. This is necessary in the case where LWR loads the full word (i.e. the address is actually aligned). In the other cases, it is implementation defined whether the upper 32 bits of the result are unchanged or a copy of bit 31. The latter seems easier to implement. Previously the code used: (oldval & (0xfffffffe << (31 - bitshift))) | (newval >> bitshift) which zeroed the upper bits of the register, losing any previous sign extension in the unaligned cases. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: Fix signedness of loads in MIPS16 RESTOREsRichard Sandiford
Make RESTORE use sign-extending rather than zero-extending loads. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno
DSP instruction from the (d)append sub-class can be implemented with TCG. Use a different function for these instructions are they are quite different from compare-pick sub-class. Fix BALIGN instruction for negative value, where the value should be zero-extended before being shift to the right. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for reduction add instructionsAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for unary DSP operatorsAurelien Jarno
This allow to reduce the number of macros. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for binary DSP operatorsAurelien Jarno
This allow to reduce the number of macros. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: add unions to access DSP elementsAurelien Jarno
Instead of playing with bit shifting, add two unions (one for 32-bit values, one for 64-bit ones) to access all the DSP elements with the correct type. This make the code easier to read and less error prone, and allow GCC to vectorize the code in some cases. Reviewed-by: Eric Johnson <ericj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: generate a reserved instruction exception on CPU without DSPAurelien Jarno
On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: copy insn_flags in DisasContextAurelien Jarno
Copy insn_flags in DisasContext to avoid passing a CPUMIPSState pointer to subroutines, as suggested by Richard Henderson. Change subroutines to use this new field and remove the first argument. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: fix DSP loads with rd = 0Aurelien Jarno
When rd is 0, which still need to do the actually load to possibly generate a TLB exception. Reviewed-by: Eric Johnson <ericj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-15exec: Return CPUState from qemu_get_cpu()Andreas Färber
Move the declaration to qemu/cpu.h and add documentation. The implementation still depends on CPUArchState for CPU iteration. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-15target-mips: Clean up mips_cpu_map_tc() documentationAndreas Färber
This function will be touched again soon, so a good understanding of env vs. other helps. Adopt gtk-doc style. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eric Johnson <ericj@mips.com>
2013-01-15cpu: Move nr_{cores,threads} fields to CPUStateAndreas Färber
To facilitate the field movements, pass MIPSCPU to malta_mips_config(); avoid that for mips_cpu_map_tc() since callers only access MIPS Thread Contexts, inside TCG helpers. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly defines halfword vector elements as unsigned values. This results in wrong output which is not triggered in the tests as they also follow this logic. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-08target-mips: Replace macros by inline functionsStefan Weil
The macros RESTORE_ROUNDING_MODE and RESTORE_FLUSH_MODE silently used variable env from their callers. Using inline functions with env passed as a function argument is more transparent. This modification was proposed by Peter Maydell. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson
Clear the DSP hflags at the start of compute_hflags. Otherwise access is not properly disabled once enabled. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Use EXCP_SC rather than a magic number陳韋任 (Wei-Ren Chen)
From the discussion on the ML [1], the exception limit defined by magic number 0x100 is actually EXCP_SC defined in cpu.h. Replace the magic number with EXCP_SC. Remove "#if 1 .. #endif" as well. [1] http://lists.gnu.org/archive/html/qemu-devel/2012-11/msg03080.html Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Make repl_ph to sign extend to target-longJovanovic, Petar
The immediate value is 9bits, should sign-extend to 16bits. The return value to register should sign-extend to target_long, as Richard says, removing an unnecessary cast works fun. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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