aboutsummaryrefslogtreecommitdiff
path: root/target-mips
AgeCommit message (Expand)Author
2007-04-28Update TODO.ths
2007-04-25Next attempt to get the lui sign extension right.ths
2007-04-25Fix lui sign extension.ths
2007-04-19Update comment. We can't easily adhere to the architecture spec becauseths
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths
2007-04-16Simplify branch likely handling.ths
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths
2007-04-15Small code generation optimization.ths
2007-04-15Delete unused define.ths
2007-04-14Restart interrupts after an exception.ths
2007-04-13Nicer Log formatting.ths
2007-04-13Another fix for CP0 Cause register handling.ths
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths
2007-04-11Throw RI for invalid MFMC0-class instructions. Introduce optionalths
2007-04-11Code formatting fix.ths
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths
2007-04-09Fix CP0_IntCtl handling.ths
2007-04-09Proper handling of reserved bits in the context register.ths
2007-04-09Mark watchpoint features as unimplemented.ths
2007-04-09Catch unaligned sc/scd.ths
2007-04-09Fix exception handling cornercase for rdhwr.ths
2007-04-09Remove bogus mtc0 handling.ths
2007-04-07Unify IRQ handling.pbrook
2007-04-07cpu_get_phys_page_debug should return target_phys_addr_tj_mayer
2007-04-07Implement prefx.ths
2007-04-07Set proper BadVAddress value for unaligned instruction fetch.ths
2007-04-07Actually skip over delay slot for a non-taken branch likely.ths
2007-04-07Fix ins/ext cornercase.ths
2007-04-06Fix handling of ADES exceptions.ths
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths
2007-04-05fix branch delay slot cornercases.ths
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths
2007-04-05Handle EBase properly.ths
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths
2007-04-0564bit MIPS FPUs have 32 registers.ths
2007-04-04Fix code formatting.ths
2007-04-02MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths
2007-04-02Build fix for 64bit machines. (This is still not correct mul/div handling.)ths
2007-04-01Actually enable 64bit configuration.ths
2007-04-01MIPS64 configurations.ths
2007-03-31Malta CBUS UART support.ths
2007-03-30Update mips TODO.ths
2007-03-30Fix typo, suggested by Ben Taylor.ths
2007-03-30Squash logic bugs while they are fresh...ths
2007-03-30Sanitize mips exception handling.ths
2007-03-24One more bit of mips CPU configuration, and support for early 4KEcths
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths
2007-03-21Move mips CPU specific initialization to translate_init.c.ths
2007-03-19Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.ths
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-22 20:44:47 +0000