Age | Commit message (Expand) | Author |
2014-11-03 | target-mips: add MSA support to mips32r5-generic | Yongbok Kim |
2014-11-03 | target-mips: add MSA MI10 format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 2RF format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA VEC/2R format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 3RF format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA ELM format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 3R format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA BIT format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA I5 format instruction | Yongbok Kim |
2014-11-03 | target-mips: add MSA I8 format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA branch instructions | Yongbok Kim |
2014-11-03 | target-mips: add msa_helper.c | Yongbok Kim |
2014-11-03 | target-mips: add msa_reset(), global msa register | Yongbok Kim |
2014-11-03 | target-mips: add MSA opcode enum | Yongbok Kim |
2014-11-03 | target-mips: stop translation after ctc1 | Yongbok Kim |
2014-11-03 | target-mips: remove duplicated mips/ieee mapping function | Yongbok Kim |
2014-11-03 | target-mips: add MSA exceptions | Yongbok Kim |
2014-11-03 | target-mips: add MSA defines and data structure | Yongbok Kim |
2014-11-03 | target-mips: enable features in MIPS64R6-generic CPU | Leon Alrae |
2014-11-03 | target-mips: correctly handle access to unimplemented CP0 register | Leon Alrae |
2014-11-03 | target-mips: add restrictions for possible values in registers | Leon Alrae |
2014-11-03 | target-mips: CP0_Status.CU0 no longer allows the user to access CP0 | Leon Alrae |
2014-11-03 | target-mips: implement forbidden slot | Leon Alrae |
2014-11-03 | target-mips: add Config5.SBRI | Leon Alrae |
2014-11-03 | target-mips: update cpu_save/cpu_load to support new registers | Leon Alrae |
2014-11-03 | target-mips: add BadInstr and BadInstrP support | Leon Alrae |
2014-11-03 | target-mips: add TLBINV support | Leon Alrae |
2014-11-03 | target-mips: add new Read-Inhibit and Execute-Inhibit exceptions | Leon Alrae |
2014-11-03 | target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1} | Leon Alrae |
2014-11-03 | target-mips: add RI and XI fields to TLB entry | Leon Alrae |
2014-11-03 | target-mips: distinguish between data load and instruction fetch | Leon Alrae |
2014-11-03 | target-mips: add KScratch registers | Leon Alrae |
2014-10-24 | target-mips: add ULL suffix in bitswap to avoid compiler warning | Leon Alrae |
2014-10-14 | target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX | Peter Maydell |
2014-10-14 | target-mips/dsp_helper.c: Add ifdef guards around various functions | Peter Maydell |
2014-10-14 | target-mips/translate.c: Add ifdef guard around check_mips64() | Peter Maydell |
2014-10-14 | target-mips/op_helper.c: Remove unused do_lbu() function | Peter Maydell |
2014-10-14 | target-mips/dsp_helper.c: Remove unused function get_DSPControl_24() | Peter Maydell |
2014-10-14 | target-mips: fix broken MIPS16 and microMIPS | Yongbok Kim |
2014-10-14 | target-mips/translate.c: Update OPC_SYNCI | Dongxue Zhang |
2014-10-14 | target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA | Leon Alrae |
2014-10-14 | target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions | Yongbok Kim |
2014-10-14 | target-mips: do not allow Status.FR=0 mode in 64-bit FPU | Leon Alrae |
2014-10-14 | target-mips: add new Floating Point Comparison instructions | Yongbok Kim |
2014-10-14 | target-mips: add new Floating Point instructions | Leon Alrae |
2014-10-14 | target-mips: add AUI, LSA and PCREL instruction families | Leon Alrae |
2014-10-13 | target-mips: add compact and CP1 branches | Yongbok Kim |
2014-10-13 | target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions | Yongbok Kim |
2014-10-13 | target-mips: Status.UX/SX/KX enable 32-bit address wrapping | Leon Alrae |
2014-10-13 | target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 | Leon Alrae |