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path: root/target-mips/translate_init.c
AgeCommit message (Expand)Author
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd
2009-12-13target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno
2009-11-14mips: fix cpu_reset memory leakBlue Swirl
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori
2009-10-01Get rid of _t suffixmalc
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
2009-03-08target-mips: rename helpers from do_ to helper_aurel32
2009-01-14target-mips: fix indentationaurel32
2009-01-12target-mips: get rid of tests on env->user_mode_onlyaurel32
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
2008-09-18Move the active FPU registers into env again, and use more TCG registersths
2008-09-14target-mips: fix warningaurel32
2008-09-02Build fix for gcc-3.3.ths
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths
2008-07-21A bunch of minor code improvements in the MIPS target.ths
2008-07-20Fix compiler warning, by Stefan Weil.ths
2008-06-27More efficient target register / TC accesses.ths
2008-05-28Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths
2008-05-06Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver.ths
2008-05-06Use TCG for MIPS GPR moves.ths
2007-12-28Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths
2007-12-25Support for VR5432, and some of its special instructions. Original patchths
2007-12-255K and 20K are Release 1 CPUs.ths
2007-12-25Improved PABITS handling, and config register fixes.ths
2007-12-24Fix CCRes value for 20Kc.ths
2007-11-19Add older 4Km variants.ths
2007-11-18Use a valid PRid.ths
2007-11-14Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths
2007-11-10added cpu_model parameter to cpu_init()bellard
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths
2007-10-29Preliminary MIPS64R2 mode.ths
2007-10-23Use the standard ASE check for MIPS-3D and MT.ths
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths
2007-09-29Supervisor mode implementation, by Aurelien Jarno.ths
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths
2007-09-23Fix mips usermode emulation.ths
2007-09-06Partial support for 34K multithreading, not functional yet.ths
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths
2007-07-29Fix MIPS cache configuration, by Aurelien Jarno.ths
2007-06-23Handle MIPS64 SEGBITS value correctly.ths
2007-06-22Allow emulation of 32bit targets in the MIPS64 capable qemu version.ths
2007-06-12Change 20Kc PRID to a later version.ths
2007-06-09R5k has PX implemented.ths
2007-06-01Update some comments, 64bit FPU support is functional regardless ofths
2007-06-01Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.ths
2007-06-01Allow again FPU for usermode emulation.ths
2007-05-30Fix CPU (re-)selection on reset.ths
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths