| Age | Commit message (Expand) | Author |
|---|
| 2009-07-16 | Update to a hopefully more future proof FSF address | Blue Swirl |
| 2009-03-08 | target-mips: rename helpers from do_ to helper_ | aurel32 |
| 2009-01-14 | target-mips: fix indentation | aurel32 |
| 2009-01-12 | target-mips: get rid of tests on env->user_mode_only | aurel32 |
| 2009-01-04 | Update FSF address in GPL/LGPL boilerplate | aurel32 |
| 2008-12-22 | Use the ARRAY_SIZE() macro where appropriate. | malc |
| 2008-09-18 | Move the active FPU registers into env again, and use more TCG registers | ths |
| 2008-09-14 | target-mips: fix warning | aurel32 |
| 2008-09-02 | Build fix for gcc-3.3. | ths |
| 2008-07-23 | Less hardcoding of TARGET_USER_ONLY. | ths |
| 2008-07-21 | A bunch of minor code improvements in the MIPS target. | ths |
| 2008-07-20 | Fix compiler warning, by Stefan Weil. | ths |
| 2008-06-27 | More efficient target register / TC accesses. | ths |
| 2008-05-28 | Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. | ths |
| 2008-05-06 | Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver. | ths |
| 2008-05-06 | Use TCG for MIPS GPR moves. | ths |
| 2007-12-28 | Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford. | ths |
| 2007-12-25 | Support for VR5432, and some of its special instructions. Original patch | ths |
| 2007-12-25 | 5K and 20K are Release 1 CPUs. | ths |
| 2007-12-25 | Improved PABITS handling, and config register fixes. | ths |
| 2007-12-24 | Fix CCRes value for 20Kc. | ths |
| 2007-11-19 | Add older 4Km variants. | ths |
| 2007-11-18 | Use a valid PRid. | ths |
| 2007-11-14 | Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP | ths |
| 2007-11-10 | added cpu_model parameter to cpu_init() | bellard |
| 2007-11-08 | Clean out the N32 macros from target-mips, and introduce MIPS ABI specific | ths |
| 2007-10-29 | Preliminary MIPS64R2 mode. | ths |
| 2007-10-23 | Use the standard ASE check for MIPS-3D and MT. | ths |
| 2007-09-30 | Code provision for n32/n64 mips userland emulation. Not functional yet. | ths |
| 2007-09-29 | Supervisor mode implementation, by Aurelien Jarno. | ths |
| 2007-09-24 | Per-CPU instruction decoding implementation, by Aurelien Jarno. | ths |
| 2007-09-23 | Fix mips usermode emulation. | ths |
| 2007-09-06 | Partial support for 34K multithreading, not functional yet. | ths |
| 2007-08-26 | Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno. | ths |
| 2007-07-29 | Fix MIPS cache configuration, by Aurelien Jarno. | ths |
| 2007-06-23 | Handle MIPS64 SEGBITS value correctly. | ths |
| 2007-06-22 | Allow emulation of 32bit targets in the MIPS64 capable qemu version. | ths |
| 2007-06-12 | Change 20Kc PRID to a later version. | ths |
| 2007-06-09 | R5k has PX implemented. | ths |
| 2007-06-01 | Update some comments, 64bit FPU support is functional regardless of | ths |
| 2007-06-01 | Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno. | ths |
| 2007-06-01 | Allow again FPU for usermode emulation. | ths |
| 2007-05-30 | Fix CPU (re-)selection on reset. | ths |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths |
| 2007-05-11 | Fix missing status ro mask initialization, thanks Stefan Weil. | ths |
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
| 2007-04-11 | Make SYNCI_Step and CCRes CPU-specific. | ths |
| 2007-04-01 | Actually enable 64bit configuration. | ths |
| 2007-03-24 | One more bit of mips CPU configuration, and support for early 4KEc | ths |
