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path: root/target-mips/translate.c
AgeCommit message (Expand)Author
2015-06-26target-mips: microMIPS32 R6 Major instructionsYongbok Kim
2015-06-26target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim
2015-06-26target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim
2015-06-26target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim
2015-06-26target-mips: microMIPS32 R6 branches and jumpsYongbok Kim
2015-06-26target-mips: add microMIPS32 R6 opcode enumYongbok Kim
2015-06-26target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim
2015-06-26target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim
2015-06-26target-mips: rearrange gen_compute_compact_branchYongbok Kim
2015-06-26target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim
2015-06-26target-mips: remove an unused argumentYongbok Kim
2015-06-26target-mips: add microMIPS TLBINV, TLBINVFYongbok Kim
2015-06-26target-mips: fix {RD, WR}PGPR in microMIPSYongbok Kim
2015-06-26target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae
2015-06-26target-mips: remove identical code in different branchLeon Alrae
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae
2015-06-12target-mips: correct MFC0 for CP0.EntryLo in MIPS64Leon Alrae
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim
2015-06-11target-mips: Misaligned memory accesses for R6Yongbok Kim
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae
2015-06-11target-mips: move group of functions above gen_load_fpr32()Leon Alrae
2015-03-18target-mips: save cpu state before calling MSA load and store helpersLeon Alrae
2015-03-18target-mips: fix hflags modified in delay / forbidden slotLeon Alrae
2015-03-18target-mips: fix CP0.BadVAddr by stopping translation on Address ErrorLeon Alrae
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-02-13target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae
2015-02-13target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae
2015-02-13target-mips: fix detection of the end of the page during translationLeon Alrae
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-02-10target-mips: Clean up switch fall through after commit fecd264Markus Armbruster
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini
2014-12-16target-mips: convert single case switch into if statementLeon Alrae
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki
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