Age | Commit message (Expand) | Author |
2007-06-02 | Check for R2 instructions, and throw RI if we don't emulate R2. | ths |
2007-06-01 | Make sure hflags are updated for CP0_Status changes. | ths |
2007-05-31 | Simplify code. | ths |
2007-05-29 | Don't check the FPU state for each FPU instruction, use hflags to | ths |
2007-05-28 | Handle PX/UX status flags correctly, by Aurelien Jarno. | ths |
2007-05-28 | MIPS64 addressing fixes, by Aurelien Jarno. | ths |
2007-05-23 | The 24k wants more watch and srsmap registers. | ths |
2007-05-23 | The previous patch to make breakpoints work was a performance | ths |
2007-05-20 | Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions. | ths |
2007-05-20 | Fix indexed FP load/store instructions. | ths |
2007-05-19 | More MIPS 64-bit FPU support. | ths |
2007-05-19 | Fix slti/sltiu for MIPS64, by Aurelien Jarno. | ths |
2007-05-19 | Fix ldl/ldr implementation, by Aurelien Jarno. | ths |
2007-05-18 | - Move FPU exception handling into helper functions, since they are big. | ths |
2007-05-18 | Work around the lack of proper handling for self-modifying code. | ths |
2007-05-13 | Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno. | ths |
2007-05-13 | Don't decode CP0 XContext on 32bit MIPS. | ths |
2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths |
2007-05-11 | Implemented cabs FP instructions, and improve exception handling for | ths |
2007-05-11 | Another bit of nicer debug output. | ths |
2007-05-11 | Implement FP madd/msub, wire up bc1any[24][ft]. | ths |
2007-05-11 | Improved debug output for the MIPS opcode decoder. | ths |
2007-05-10 | Fix for the scd instruction, by Aurelien Jarno. | ths |
2007-05-09 | Fix MIPS64 address computation specialcase, by Aurelien Jarno. | ths |
2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths |
2007-04-25 | Next attempt to get the lui sign extension right. | ths |
2007-04-25 | Fix lui sign extension. | ths |
2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
2007-04-16 | Simplify branch likely handling. | ths |
2007-04-15 | Don't use T2 for INS, it conflicts with branch delay slot handling. | ths |
2007-04-15 | Small code generation optimization. | ths |
2007-04-14 | Restart interrupts after an exception. | ths |
2007-04-11 | Make SYNCI_Step and CCRes CPU-specific. | ths |
2007-04-11 | Throw RI for invalid MFMC0-class instructions. Introduce optional | ths |
2007-04-11 | Code formatting fix. | ths |
2007-04-11 | More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may | ths |
2007-04-09 | Fix CP0_IntCtl handling. | ths |
2007-04-09 | Mark watchpoint features as unimplemented. | ths |
2007-04-09 | Catch unaligned sc/scd. | ths |
2007-04-09 | Fix exception handling cornercase for rdhwr. | ths |
2007-04-09 | Remove bogus mtc0 handling. | ths |
2007-04-07 | Implement prefx. | ths |
2007-04-07 | Set proper BadVAddress value for unaligned instruction fetch. | ths |
2007-04-07 | Actually skip over delay slot for a non-taken branch likely. | ths |
2007-04-06 | Save state for all CP0 instructions, they may throw a CPU exception. | ths |
2007-04-05 | fix branch delay slot cornercases. | ths |
2007-04-05 | Fix rotr immediate ops, mask shift/rotate arguments to their allowed | ths |
2007-04-05 | Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise | ths |
2007-04-04 | Fix code formatting. | ths |
2007-04-02 | MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers | ths |