Age | Commit message (Expand) | Author |
2015-03-13 | tcg: Change translator-side labels to a pointer | Richard Henderson |
2015-02-13 | target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction | Leon Alrae |
2015-02-13 | target-mips: use CP0EnLo_XI instead of magic number | Leon Alrae |
2015-02-13 | target-mips: fix detection of the end of the page during translation | Leon Alrae |
2015-02-12 | tcg: Introduce tcg_op_buf_count and tcg_op_buf_full | Richard Henderson |
2015-02-12 | tcg: Move emit of INDEX_op_end into gen_tb_end | Richard Henderson |
2015-02-10 | target-mips: Clean up switch fall through after commit fecd264 | Markus Armbruster |
2015-01-03 | gen-icount: check cflags instead of use_icount global | Paolo Bonzini |
2015-01-03 | translate: check cflags instead of use_icount global | Paolo Bonzini |
2014-12-16 | target-mips: convert single case switch into if statement | Leon Alrae |
2014-12-16 | target-mips: Fix DisasContext's ulri member initialization | Maciej W. Rozycki |
2014-12-16 | target-mips: Add missing calls to synchronise SoftFloat status | Maciej W. Rozycki |
2014-12-16 | target-mips: Correct 32-bit address space wrapping | Maciej W. Rozycki |
2014-12-16 | target-mips: Tighten ISA level checks | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix CP0.Config3.ISAOnExc write accesses | Maciej W. Rozycki |
2014-12-16 | target-mips: Output CP0.Config2-5 in the register dump | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP | Maciej W. Rozycki |
2014-12-16 | target-mips: Correct MIPS16/microMIPS branch size calculation | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix formatting in `decode_opc' | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix formatting in `decode_extended_mips16_opc' | Maciej W. Rozycki |
2014-11-07 | target-mips: fix multiple TCG registers covering same data | Yongbok Kim |
2014-11-07 | mips: Ensure PC update with MTC0 single-stepping | Maciej W. Rozycki |
2014-11-07 | target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ | Leon Alrae |
2014-11-07 | mips: Respect CP0.Status.CU1 for microMIPS FP branches | Maciej W. Rozycki |
2014-11-03 | target-mips: add MSA MI10 format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 2RF format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA VEC/2R format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 3RF format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA ELM format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA 3R format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA BIT format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA I5 format instruction | Yongbok Kim |
2014-11-03 | target-mips: add MSA I8 format instructions | Yongbok Kim |
2014-11-03 | target-mips: add MSA branch instructions | Yongbok Kim |
2014-11-03 | target-mips: add msa_reset(), global msa register | Yongbok Kim |
2014-11-03 | target-mips: add MSA opcode enum | Yongbok Kim |
2014-11-03 | target-mips: stop translation after ctc1 | Yongbok Kim |
2014-11-03 | target-mips: correctly handle access to unimplemented CP0 register | Leon Alrae |
2014-11-03 | target-mips: implement forbidden slot | Leon Alrae |
2014-11-03 | target-mips: add Config5.SBRI | Leon Alrae |
2014-11-03 | target-mips: add BadInstr and BadInstrP support | Leon Alrae |
2014-11-03 | target-mips: add TLBINV support | Leon Alrae |
2014-11-03 | target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1} | Leon Alrae |
2014-11-03 | target-mips: add KScratch registers | Leon Alrae |
2014-10-14 | target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX | Peter Maydell |
2014-10-14 | target-mips/translate.c: Add ifdef guard around check_mips64() | Peter Maydell |
2014-10-14 | target-mips: fix broken MIPS16 and microMIPS | Yongbok Kim |
2014-10-14 | target-mips/translate.c: Update OPC_SYNCI | Dongxue Zhang |
2014-10-14 | target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions | Yongbok Kim |
2014-10-14 | target-mips: do not allow Status.FR=0 mode in 64-bit FPU | Leon Alrae |