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2009-01-14target-mips: optimize some gpr accessesaurel32
Optimize gpr accesses when it is known at translation time that gpr != 0. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6307 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14target-mips: fix indentationaurel32
Remove all tabs from target-mips/* Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12target-mips: get rid of tests on env->user_mode_onlyaurel32
Replace runtime checks on env->user_mode_only by compile time checks on CONFIG_USER_ONLY. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6276 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the code and also fixing a use after release issue in cpu_break/watchpoint_remove_all. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the succeeding enhancements this series comes with. First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching to dynamically allocated data structures that are kept in linked lists. This also allows to return a stable reference to the related objects, required for later introduced x86 debug register support. Breakpoints and watchpoints are stored with their full information set and an additional flag field that makes them easily extensible for use beyond pure guest debugging. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-15target-mips: avoid tcg internal error in mfc0/dmfc0aurel32
Set t0 to 0 for unimplemented mfc0/dmfc0 instructions. This fixes a tcg internal error while booting mips linux. Noticed by Julia Longtin. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5723 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11Revert commits 5685 to 5688 committed by mistakeaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5691 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11Don't stop translation for mtc0 compareaurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5686 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: gen_compute_branch1()aurel32
Optimize code generation in gen_compute_branch1(): - Directly use I32 variables instead of converting values from _tl to _i32 and back to _tl. - Write the result directly to bcond instead of passing by a local variable. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5684 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize movc*()aurel32
Optimize code generation in gen_movc*(): - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. - Avoid using temporary variables to transfer values. - Access fpu_fcr31 directly in gen_movcf_ps(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5683 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_farith()aurel32
Optimize code generation in gen_farith(): - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5682 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_muldiv()aurel32
Optimize code generation in gen_muldiv(): - Don't do sign extension when the value is already guaranteed to be sign extended (otherwise, results are marked as UNPREDICTABLE). - Access the LO, HI registers directly instead of writting them through a temporary variable. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5681 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_arith()/gen_arith_imm()aurel32
Optimize code generation in gen_arith()/gen_arith_imm(): - Don't do sign extension when the value is already guaranteed to be sign extended (otherwise, results are marked as UNPREDICTABLE). - When the value is sign extended, compare the value to 0 instead of testing bit 31/63. - Temp variables are valid up to and *including* the brcond instruction. Use them instead of temp local variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5680 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: convert bit shuffle ops to TCGaurel32
Bit shuffle operations can be written with very few TCG instructions (between 5 and 8), so it is worth converting them to TCG. This code also move all bit shuffle generation code to a separate function in order to have a cleaner exception code path, that is it doesn't store back the TCG register to the target register after the exception, as the TCG register doesn't exist anymore. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5679 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: convert bitfield ops to TCGaurel32
Bitfield operations can be written with very few TCG instructions (between 2 and 5), so it is worth converting them to TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_op_addr_add() (2/2)aurel32
Instead of dynamically generating different code depending on the UX flag, add a new flag in ctx->flags to generate different code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_op_addr_add() (1/2)aurel32
The user mode can be tested at translation time using ctx->hflags. This simplifies gen_op_addr_add(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5676 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: optimize gen_save_pc()aurel32
We obviously don't need to use a temporary variable to write PC. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5675 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: fix mft* helpers/callaurel32
This patch attempts to fix mft* helpers and the associated TCG calls. mft* helpers do not take a register in argument, however: - some helpers are called with an argument while they do not take one. - some helpers are declared with an argument they don't use. Acked-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5674 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-mips: fix temporary variable freeing in op_ldst_##insn()aurel32
Move tcg_temp_free() out of the conditional part to make sure the TCG temporary variable is freed in all cases. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5673 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-04target-mips: use the new rotr/rotri instructionsaurel32
Acked-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5622 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22Use concet TCG instructions in the MIPS target.ths
Signed-off-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5303 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21Add concat_i32_i64 op.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18Use TCG registers for most CPU register accesses.ths
Signed-off-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5253 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18Move the active FPU registers into env again, and use more TCG registersths
to access them. Signed-off-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05TCG fixes for target-mipsaurel32
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-23MIPS: don't free TCG temporary variable twiceaurel32
In gen_dmtc0 function, TCG temporary variable t0 is freed at the end of the function. Variable is freed again in the gen_dmtc0 caller. I removed the free in gen_dmtc0, to do like in gen_dmfc0, gen_mfc0, gen_mtc0. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5075 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-01Delete unused variable.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4981 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-21A bunch of minor code improvements in the MIPS target.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4921 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-21Fix logging output for MIPS HI, LO registers, by Stefan Weil.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4916 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-20Simplify conditional FP moves.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4913 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-09Use temporary registers for the MIPS FPU emulation.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-05Fix typo in comment.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4852 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01Static'ify some functions, and use standard inline in translate.c.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4813 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01Delete duplicate code.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4811 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30Spelling fixes, spotted by Stuart Brady.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30Make bcond and btarget TCG registers.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4805 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29Remove unnecessary helper arguments, and fix some typos.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4802 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29Add missing file. Fix spelling errors.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4800 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29Add instruction counter.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27Avoid unused input arguments which triggered tcg errors. Spotted byths
Stefan Weil. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27More efficient target register / TC accesses.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24Remove remaining uses of T0 in the MIPS target.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24T1 is now dead.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24Reduce use of fixed registers a bit more.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4786 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24Use temporaries instead of fixed registers for some instructions.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
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