aboutsummaryrefslogtreecommitdiff
path: root/target-mips/translate.c
AgeCommit message (Expand)Author
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-02-13target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae
2015-02-13target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae
2015-02-13target-mips: fix detection of the end of the page during translationLeon Alrae
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-02-10target-mips: Clean up switch fall through after commit fecd264Markus Armbruster
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini
2014-12-16target-mips: convert single case switch into if statementLeon Alrae
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki
2014-11-07target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae
2014-11-07mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim
2014-11-03target-mips: add MSA branch instructionsYongbok Kim
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim
2014-11-03target-mips: add MSA opcode enumYongbok Kim
2014-11-03target-mips: stop translation after ctc1Yongbok Kim
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae
2014-11-03target-mips: implement forbidden slotLeon Alrae
2014-11-03target-mips: add Config5.SBRILeon Alrae
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae
2014-11-03target-mips: add TLBINV supportLeon Alrae
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae
2014-11-03target-mips: add KScratch registersLeon Alrae
2014-10-14target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell
2014-10-14target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim
2014-10-14target-mips/translate.c: Update OPC_SYNCIDongxue Zhang
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim
2014-10-14target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 23:01:10 +0000