Age | Commit message (Expand) | Author |
2015-06-26 | target-mips: microMIPS32 R6 Major instructions | Yongbok Kim |
2015-06-26 | target-mips: microMIPS32 R6 POOL32{I, C} instructions | Yongbok Kim |
2015-06-26 | target-mips: microMIPS32 R6 POOL32F instructions | Yongbok Kim |
2015-06-26 | target-mips: microMIPS32 R6 POOL32A{XF} instructions | Yongbok Kim |
2015-06-26 | target-mips: microMIPS32 R6 branches and jumps | Yongbok Kim |
2015-06-26 | target-mips: add microMIPS32 R6 opcode enum | Yongbok Kim |
2015-06-26 | target-mips: signal RI for removed instructions in microMIPS R6 | Yongbok Kim |
2015-06-26 | target-mips: raise RI exceptions when FIR.PS = 0 | Yongbok Kim |
2015-06-26 | target-mips: rearrange gen_compute_compact_branch | Yongbok Kim |
2015-06-26 | target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP | Yongbok Kim |
2015-06-26 | target-mips: remove an unused argument | Yongbok Kim |
2015-06-26 | target-mips: add microMIPS TLBINV, TLBINVF | Yongbok Kim |
2015-06-26 | target-mips: fix {RD, WR}PGPR in microMIPS | Yongbok Kim |
2015-06-26 | target-mips: add Unified Hosting Interface (UHI) support | Leon Alrae |
2015-06-26 | target-mips: remove identical code in different branch | Leon Alrae |
2015-06-22 | disas: Remove uses of CPU env | Peter Crosthwaite |
2015-06-12 | target-mips: add MTHC0 and MFHC0 instructions | Leon Alrae |
2015-06-12 | target-mips: add CP0.PageGrain.ELPA support | Leon Alrae |
2015-06-12 | target-mips: extend selected CP0 registers to 64-bits in MIPS32 | Leon Alrae |
2015-06-12 | target-mips: correct MFC0 for CP0.EntryLo in MIPS64 | Leon Alrae |
2015-06-11 | target-mips: add ERETNC instruction and Config5.LLB bit | Leon Alrae |
2015-06-11 | target-mips: Misaligned memory accesses for MSA | Yongbok Kim |
2015-06-11 | target-mips: Misaligned memory accesses for R6 | Yongbok Kim |
2015-06-11 | target-mips: add Config5.FRE support allowing Status.FR=0 emulation | Leon Alrae |
2015-06-11 | target-mips: move group of functions above gen_load_fpr32() | Leon Alrae |
2015-03-18 | target-mips: save cpu state before calling MSA load and store helpers | Leon Alrae |
2015-03-18 | target-mips: fix hflags modified in delay / forbidden slot | Leon Alrae |
2015-03-18 | target-mips: fix CP0.BadVAddr by stopping translation on Address Error | Leon Alrae |
2015-03-13 | tcg: Change translator-side labels to a pointer | Richard Henderson |
2015-02-13 | target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction | Leon Alrae |
2015-02-13 | target-mips: use CP0EnLo_XI instead of magic number | Leon Alrae |
2015-02-13 | target-mips: fix detection of the end of the page during translation | Leon Alrae |
2015-02-12 | tcg: Introduce tcg_op_buf_count and tcg_op_buf_full | Richard Henderson |
2015-02-12 | tcg: Move emit of INDEX_op_end into gen_tb_end | Richard Henderson |
2015-02-10 | target-mips: Clean up switch fall through after commit fecd264 | Markus Armbruster |
2015-01-03 | gen-icount: check cflags instead of use_icount global | Paolo Bonzini |
2015-01-03 | translate: check cflags instead of use_icount global | Paolo Bonzini |
2014-12-16 | target-mips: convert single case switch into if statement | Leon Alrae |
2014-12-16 | target-mips: Fix DisasContext's ulri member initialization | Maciej W. Rozycki |
2014-12-16 | target-mips: Add missing calls to synchronise SoftFloat status | Maciej W. Rozycki |
2014-12-16 | target-mips: Correct 32-bit address space wrapping | Maciej W. Rozycki |
2014-12-16 | target-mips: Tighten ISA level checks | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix CP0.Config3.ISAOnExc write accesses | Maciej W. Rozycki |
2014-12-16 | target-mips: Output CP0.Config2-5 in the register dump | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP | Maciej W. Rozycki |
2014-12-16 | target-mips: Correct MIPS16/microMIPS branch size calculation | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix formatting in `decode_opc' | Maciej W. Rozycki |
2014-12-16 | target-mips: Fix formatting in `decode_extended_mips16_opc' | Maciej W. Rozycki |
2014-11-07 | target-mips: fix multiple TCG registers covering same data | Yongbok Kim |
2014-11-07 | mips: Ensure PC update with MTC0 single-stepping | Maciej W. Rozycki |