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2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim
Avoid to allocate different TCG registers for the FPU registers that are mapped on the MSA vectore registers. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki
Correct the way PC is updated when single-stepping instructions, by keeping the old PC only for the BS_EXCP (exception condition) state. Some MTC0 (and possibly other) instructions switch to the BS_STOP state to terminate the current translation block, so that the state transition of the simulated CPU resulting from the CP0 operation takes effect with the following instruction. This happens with `mtc0 <reg>,c0_config' for example, typically used to set KSEG0 cacheability. While single-stepping this has a side-effect of not advancing the PC past the instruction just executed; subsequent single-step traps will stop at the same instruction repeatedly. Example: (gdb) stepi 0x80004d24 in _start () 5: x/i $pc => 0x80004d24 <_start+364>: mfc0 t1,c0_config (gdb) 0x80004d28 in _start () 5: x/i $pc => 0x80004d28 <_start+368>: li at,-8 (gdb) 0x80004d2c in _start () 5: x/i $pc => 0x80004d2c <_start+372>: and t1,t1,at (gdb) 0x80004d30 in _start () 5: x/i $pc => 0x80004d30 <_start+376>: ori t1,t1,0x3 (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) 0x80004d34 in _start () 5: x/i $pc => 0x80004d34 <_start+380>: mtc0 t1,c0_config (gdb) -- oops! Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-07target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae
New R6 COP1 conditional branches currently don't have delay slot. Fixing this by setting MIPS_HFLAG_BDS32 flag which is required for branches having 4-byte delay slot. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-07mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki
Make microMIPS FP branches respect CP0.Status.CU1 and trap with a Coprocessor Unusable exception if COP1 has been disabled; also trap if no FPU is present at all. Standard MIPS FP instruction encodings have a more regular structure and branches are covered with a single umbrella along other instructions. This is not the case with the microMIPS encoding, this case has to be taken care of explicitly here. Code to do so has been copied from the standard MIPS code handler for OPC_CP1, in `decode_opc'. Problems arising from this bug will generally only show up on user context switches in operating systems making use of lazy FP context switches, such as Linux. It will also more readily trigger if software FPU emulation is used, either implicitly on a non-float CPU, or forced on a hard-float CPU such as with the "nofpu" Linux kernel command line argument. The problem may have been easily missed because we have no hard-float microMIPS CPU configuration present; in fact we have no microMIPS CPU configuration of any kind present. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim
add MSA MI10 format instructions update LSA and DLSA for MSA add 16, 64 bit load and store Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim
add MSA 2RF format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim
add MSA VEC/2R format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim
add MSA 3RF format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim
add MSA ELM format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim
add MSA 3R format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim
add MSA BIT format instructions Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim
add MSA I5 format instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim
add MSA I8 format instructions Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA branch instructionsYongbok Kim
add MSA branch instructions Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim
add msa_reset() and global msa register (d type only) Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA opcode enumYongbok Kim
add MSA opcode enum Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: stop translation after ctc1Yongbok Kim
stop translation as ctc1 instruction can change hflags Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae
Release 6 limits the number of cases where software can cause UNDEFINED or UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented CP0 register, writes are ignored and reads return 0. In pre-R6 the behaviour is not specified, but generating RI exception is not what the real HW does. Additionally, remove CP0 Random register as it became reserved in Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: implement forbidden slotLeon Alrae
When conditional compact branch is encountered decode one more instruction in current translation block - that will be forbidden slot. Instruction in forbidden slot will be executed only if conditional compact branch is not taken. Any control transfer instruction (CTI) which are branches, jumps, ERET, DERET, WAIT and PAUSE will generate RI exception if executed in forbidden or delay slot. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add Config5.SBRILeon Alrae
SDBBP instruction Reserved Instruction control. The purpose of this field is to restrict availability of SDBBP to kernel mode operation. If the bit is set then SDBBP instruction can only be executed in kernel mode. User execution of SDBBP will cause a Reserved Instruction exception. Additionally add missing Config4 and Config5 cases for dm{f,t}c0. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae
BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register contains the prior branch instruction, when the faulting instruction is in a branch delay slot. Using error_code to indicate whether AdEL or TLBL was triggered during instruction fetch, in this case BadInstr is not updated as valid instruction word is not available. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add TLBINV supportLeon Alrae
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae
PageGrain needs rw bitmask which differs between MIPS architectures. In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable, whereas in R6 they are read-only 1. On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward compatiblity, therefore there are separate mtc0 and dmtc0 helpers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add KScratch registersLeon Alrae
KScratch<n> Registers (CP0 Register 31, Selects 2 to 7) The KScratch registers are read/write registers available for scratch pad storage by kernel mode software. They are 32-bits in width for 32-bit processors and 64-bits for 64-bit processors. CP0Config4.KScrExist[2:7] bits indicate presence of CP0_KScratch1-6 registers. For Release 6, all KScratch registers are required. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-14target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell
Remove the functions gen_load_ACX and gen_store_ACX, which appear to have been unused since they were first introduced many years ago. These functions were the only places using the cpu_ACX[] array of TCG globals, so remove that and its accompanying regnames_ACX[] as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-14target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell
The function check_mips64() is only used if TARGET_MIPS64 is defined; add an ifdef guard to its definition to avoid warnings about it being unused in other configurations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim
Commit 240ce26a broke MIPS16 and microMIPS support as it didn't care those branches and jumps don't have delay slot in MIPS16 and microMIPS. This patch introduces a new argument delayslot_size to the gen_compute_branch() indicating size of delay slot {0, 2, 4}. And the information is used to call handle_delay_slot() forcingly when no delay slot is required. There are some microMIPS branch and jump instructions that requires exact size of instruction in the delay slot. For indicating these instructions, MIPS_HFLAG_BDS_STRICT flag is introduced. Those fictional branch opcodes defined to support MIPS16 and microMIPS are no longer needed. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Tested-by: Jonas Gorski <jogo@openwrt.org> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: cosmetic changes] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-14target-mips/translate.c: Update OPC_SYNCIDongxue Zhang
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved in the same TB of the store instruction. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: update microMIPS SYNCI as well] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-14target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae
Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae
In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-14target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-13target-mips: add compact and CP1 branchesYongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot - they have forbidden slot instead. However, current implementation does not support forbidden slot yet. Add also BC1EQZ and BC1NEZ instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae
In R6 the special behaviour for data references is also specified for Kernel and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae
Use "R6_" prefix in front of all new Multiply / Divide instructions for easier differentiation between R6 and preR6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6. Additionally, the hint codes in PREF instruction greater than or equal to 24 generate Reserved Instruction Exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: signal RI Exception on DSP and Loongson instructionsLeon Alrae
Move DSP and Loongson instruction to *_legacy functions as they have been removed in R6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: split decode_opc_special* into *_r6 and *_legacyLeon Alrae
For better code readability and to avoid 'if' statements for all R6 and preR6 instructions whose opcodes are the same - decode_opc_special* functions are split into functions with _r6 and _legacy suffixes. *_r6 functions will contain instructions which were introduced in R6. *_legacy functions will contain instructions which were removed in R6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: extract decode_opc_special* from decode_opcLeon Alrae
Creating separate decode functions for special, special2 and special3 instructions to ease adding new R6 instructions and removing legacy instructions. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move LL and SC instructionsLeon Alrae
The encoding of LL and SC instruction has changed in MIPS32 Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
2014-10-13target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
2014-10-13target-mips: signal RI Exception on instructions removed in R6Leon Alrae
Signal Reserved Instruction Exception on instructions that do not exist in R6. In this commit the following groups of preR6 instructions are marked as deleted: - Floating Point Paired Single - Floating Point Compare - conditional moves / branches on FPU conditions - branch likelies - unaligned loads / stores - traps - legacy accumulator instructions - COP1X - MIPS-3D Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-07-28target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang
Free t0 and t1 in opcode OPC_DINSV. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2014-07-05mips/kvm: Init EBase to correct KSEG0James Hogan
The EBase CP0 register is initialised to 0x80000000, however with KVM the guest's KSEG0 is at 0x40000000. The incorrect value doesn't get passed to KVM yet as KVM doesn't implement the EBase register, however we should set it correctly now so as not to break migration/loadvm to a future version of QEMU that does support EBase. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-20target-mips: copy CP0_Config1 into DisasContextAurelien Jarno
In order to avoid access to the CPUMIPSState structure in the translator, keep a copy of CP0_Config1 into DisasContext. The whole register is read-only so it can be copied as a single value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2014-06-20Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell
* remotes/kvm/uq/master: hw/mips: malta: Don't boot from flash with KVM T&E MAINTAINERS: Add entry for MIPS KVM target-mips: Enable KVM support in build system hw/mips: malta: Add KVM support hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctls target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() target-mips: kvm: Add main KVM support for MIPS kvm: Allow arch to set sigmask length target-mips: get_physical_address: Add KVM awareness target-mips: get_physical_address: Add defines for segment bases hw/mips: Add API to convert KVM guest KSEG0 <-> GPA hw/mips/cputimer: Don't start periodic timer in KVM mode target-mips: Reset CPU timer consistently KVM: Fix GSI number space limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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