aboutsummaryrefslogtreecommitdiff
path: root/target-mips/translate.c
AgeCommit message (Collapse)Author
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber
Turn cpu_init macro into a static inline function returning CPUMIPSState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ify CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the introduction of subclasses for 1.1, due to mips_def_t the reset code could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to CPUClass::reset(). Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling cpu_state_reset(), so that generic code can be converted to call cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber
Move code not dependent on mips_def_t from cpu_mips_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30target-mips: QOM'ify CPUAndreas Färber
Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-28target-mips: Clean includesStefan Weil
Remove some include statements which are not needed. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2011-09-06mips: Initialize MT state at resetEdgar E. Iglesias
Only TC0 on VPE0 is active after reset. All other VPEs and TCs start in sleep. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil
tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-24target-mips: fix save_cpu_state() callsAurelien Jarno
The rule is: - don't save PC if the exception is only triggered by softmmu. - save PC if the exception can be triggered by an helper. Fix a 64-bit kernel crash when loading modules. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-18mips: Break TBs after mfc0_countEdgar E. Iglesias
Break the TB after reading the count register. This makes it possible to take timer interrupts immediately after a read of a possibly expired timer. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-12-22target-mips: fix translation of MT instructionsNathan Froyd
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of: int x; ... /* no initialization of x */ x = f (x); which confused later bits of TCG rather badly, leading to crashes. Fix the helpers to only return results (those instructions have no inputs), and fix the translation code accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-13mips: avoid write only variablesBlue Swirl
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like: /src/qemu/target-mips/translate.c: In function 'gen_ld': /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-31Correctly identify multiple cpus in SMP systemsHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-25mips: more fixes to the MIPS interrupt glue logicAurelien Jarno
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-11target-mips: add loongson 2E & 2F integer instructionsAurelien Jarno
This patch adds support for loongson 2E & 2F instructions. They are the same instructions, but differ by the opcode encoding. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-mips: add Loongson support prefetchAurelien Jarno
Loongson CPU uses a load to zero register for prefetch. Emulate it as a NOP. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-mips: split load and storeAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30target-mips: fix DINSU instructionAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29target-mips: enable movn/movz on loongson 2E & 2FAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: Fix compilationStefan Weil
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32. Cc: Nathan Froyd <froydnj@codesourcery.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: microMIPS ASE supportNathan Froyd
Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: mips16 cleanupsNathan Froyd
Change code handling mips16-specific branches to use ISA-neutral special opcodes. Since there are several places where the delay slot requirements for microMIPS branches differ from mips16 branches, using opcodes is easier than checking hflags, then checking mips16 vs. microMIPS. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: refactor c{, abs}.cond.fmt insnsNathan Froyd
Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: move FP FMT comments closer to the definitionsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: define constants for magic numbersNathan Froyd
Add FMT_* constants for the floating-point format field in opcodes and tweak a few places to use them. Add enums for various invocations of FOP and tweak gen_farith and its lone caller accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08target-mips: break out [ls][wd]c1 and rdhwr insn generationNathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05target-mips: Remove duplicate CPU log.Richard Henderson
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09target-mips: Fix format specifiers for fpu_fprintfStefan Weil
In the previous patch which introduced fprintf_function to allow parameter checking by gcc some compiler warnings remained unfixed. These warnings are fixed here. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-mips: Fix one more format specifier for cpu_fprintfStefan Weil
env->bcond must be printed using TARGET_FMT_ld. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-04target-mips: use newer logical opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02target-mips: use setcond when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: fix ROTR and DROTR by zeroNathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: fix CpU exception for coprocessor 0Nathan Froyd
When we signal a CpU exception for coprocessor 0, we should indicate that it's for coprocessor 0 instead of coprocessor 1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: remove useless sign extensionAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd
Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add copyright notice for mips16 workNathan Froyd
Also cross off mips16 ASE in TODO. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add mips16 instruction decodingNathan Froyd
There's no good way to add this incrementally, so we do it all at once. The only changes to shared code are in handle_delay_slot. We need to flip ISAMode when doing a jump-and-exchange. We also need to set ISAMode the low bit of the target address for jump-to-register. Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT, make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want basic information about a branch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add enums for MIPS16 opcodesNathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: split out delay slot handlingNathan Froyd
Move delay slot handling to common code whose invocation can be controlled from gen_intermediate_code_internal. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add gen_base_offset_addrNathan Froyd
This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: make gen_compute_branch 16/32-bit-awareNathan Froyd
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: move ROTR and ROTRV inside gen_shift_{imm, }Nathan Froyd
It's easier to implement mips16 shift instructions if we're not examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV and do the special-case handling of SRL and SRLV inside decode_opc. Likewise for their 64-bit counterparts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-16 08:26:41 +0000