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path: root/target-mips/translate.c
AgeCommit message (Expand)Author
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno
2012-10-31target-mips: optimize load operationsAurelien Jarno
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu
2012-10-31Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu
2012-10-28target-mips: Use TCG registers for the FPU.Richard Henderson
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson
2012-09-19target-mips: Always evaluate debugging macro argumentsRichard Henderson
2012-09-19target-mips: Fix MIPS_DEBUG.Richard Henderson
2012-09-19target-mips: Set opn in gen_ldst_multiple.Richard Henderson
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson
2012-08-27target-mips: Streamline indexed cp1 memory addressing.Richard Henderson
2012-08-27Fix order of CVT.PS.S operandsRichard Sandiford
2012-08-27Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford
2012-08-23target-mips: Enable access to required RDHWR hardware registersMeador Inge
2012-08-09MIPS: Correct FCR0 initializationNathan Froyd
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber
2012-04-30target-mips: QOM'ify CPUAndreas Färber
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
2012-02-28target-mips: Clean includesStefan Weil
2011-09-06mips: Initialize MT state at resetEdgar E. Iglesias
2011-09-06mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
2011-06-26Remove exec-all.h include directivesBlue Swirl
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil
2011-01-24target-mips: fix save_cpu_state() callsAurelien Jarno
2011-01-18mips: Break TBs after mfc0_countEdgar E. Iglesias
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