| Age | Commit message (Expand) | Author |
|---|
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths |
| 2007-04-25 | Next attempt to get the lui sign extension right. | ths |
| 2007-04-25 | Fix lui sign extension. | ths |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
| 2007-04-16 | Simplify branch likely handling. | ths |
| 2007-04-15 | Don't use T2 for INS, it conflicts with branch delay slot handling. | ths |
| 2007-04-15 | Small code generation optimization. | ths |
| 2007-04-14 | Restart interrupts after an exception. | ths |
| 2007-04-11 | Make SYNCI_Step and CCRes CPU-specific. | ths |
| 2007-04-11 | Throw RI for invalid MFMC0-class instructions. Introduce optional | ths |
| 2007-04-11 | Code formatting fix. | ths |
| 2007-04-11 | More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may | ths |
| 2007-04-09 | Fix CP0_IntCtl handling. | ths |
| 2007-04-09 | Mark watchpoint features as unimplemented. | ths |
| 2007-04-09 | Catch unaligned sc/scd. | ths |
| 2007-04-09 | Fix exception handling cornercase for rdhwr. | ths |
| 2007-04-09 | Remove bogus mtc0 handling. | ths |
| 2007-04-07 | Implement prefx. | ths |
| 2007-04-07 | Set proper BadVAddress value for unaligned instruction fetch. | ths |
| 2007-04-07 | Actually skip over delay slot for a non-taken branch likely. | ths |
| 2007-04-06 | Save state for all CP0 instructions, they may throw a CPU exception. | ths |
| 2007-04-05 | fix branch delay slot cornercases. | ths |
| 2007-04-05 | Fix rotr immediate ops, mask shift/rotate arguments to their allowed | ths |
| 2007-04-05 | Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise | ths |
| 2007-04-04 | Fix code formatting. | ths |
| 2007-04-02 | MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers | ths |
| 2007-04-01 | Actually enable 64bit configuration. | ths |
| 2007-03-30 | Sanitize mips exception handling. | ths |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths |
| 2007-03-21 | Move mips CPU specific initialization to translate_init.c. | ths |
| 2007-03-19 | Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil. | ths |
| 2007-03-19 | Define gen_intermediate_code_internal as "static inline". | ths |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths |
| 2007-03-02 | MIPS Userland TLS register emulation, by Daniel Jacobowitz. | ths |
| 2007-02-28 | MIPS FPU dynamic activation, part 1, by Herve Poussineau. | ths |
| 2007-02-27 | Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. | ths |
| 2007-02-20 | Replace TLSZ with TARGET_FMT_lx. | ths |
| 2007-01-24 | EBase is limited to KSEG0/KSEG1 even on 64bit CPUs. | ths |
| 2007-01-23 | Implementing dmfc/dmtc. | ths |
| 2006-12-21 | Scrap SIGN_EXTEND32. | ths |
| 2006-12-21 | Preliminiary MIPS64 support, disabled by default due to performance impact. | ths |
| 2006-12-16 | Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto. | ths |
| 2006-12-10 | Handle invalid accesses as SIGILL for mips/mipsel userland emulation. | ths |
| 2006-12-07 | Fix build of MIPS target without FPU support. | ths |
| 2006-12-07 | Fix reset handling, CP0 isn't enabled by default (a fact which doesn't | ths |
| 2006-12-07 | Simplify mask construction. | ths |
| 2006-12-06 | Update copyright notice. | ths |
| 2006-12-06 | Add MIPS32R2 instructions, and generally straighten out the instruction | ths |
| 2006-12-06 | Dynamically translate MIPS mtc0 instructions. | ths |
| 2006-12-06 | Dynamically translate MIPS mfc0 instructions. | ths |
