| Age | Commit message (Expand) | Author |
|---|
| 2007-09-24 | Per-CPU instruction decoding implementation, by Aurelien Jarno. | ths |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths |
| 2007-04-29 | Kill broken host register definitions, thanks to Paul Brook and Herve | ths |
| 2007-04-19 | Update comment. We can't easily adhere to the architecture spec because | ths |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
| 2007-04-11 | Throw RI for invalid MFMC0-class instructions. Introduce optional | ths |
| 2007-04-01 | Actually enable 64bit configuration. | ths |
| 2007-03-21 | Move mips CPU specific initialization to translate_init.c. | ths |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths |
| 2007-02-28 | MIPS FPU dynamic activation, part 1, by Herve Poussineau. | ths |
| 2006-12-21 | Preliminiary MIPS64 support, disabled by default due to performance impact. | ths |
| 2006-12-06 | Add MIPS32R2 instructions, and generally straighten out the instruction | ths |
| 2006-12-06 | MIPS TLB performance improvements, by Daniel Jacobowitz. | ths |
| 2006-06-14 | mips config fixes (initial patch by Stefan Weil) | bellard |
| 2006-06-14 | MIPS FPU support (Marius Goeger) | bellard |
| 2005-07-02 | MIPS target (Jocelyn Mayer) | bellard |
