Age | Commit message (Expand) | Author |
2016-07-12 | target-*: Clean up cpu.h header guards | Markus Armbruster |
2016-07-12 | Fix confusing argument names in some common functions | Sergey Sorokin |
2016-07-12 | target-mips: support CP0.Config4.AE bit | Paul Burton |
2016-07-12 | target-mips: change ASID type to hold more than 8 bits | Paul Burton |
2016-07-12 | target-mips: add ASID mask field and replace magic values | Paul Burton |
2016-07-12 | target-mips: add exception base to MIPS CPU | Leon Alrae |
2016-06-29 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2016-06-29 | target-*: Don't redefine cpu_exec() | Peter Crosthwaite |
2016-06-24 | target-mips: Add FCR31's FS bit definition | Aleksandar Markovic |
2016-06-24 | target-mips: Implement FCR31's R/W bitmask and related functionalities | Aleksandar Markovic |
2016-06-24 | softfloat: Implement run-time-configurable meaning of signaling NaN bit | Aleksandar Markovic |
2016-05-19 | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini |
2016-05-19 | mips: move CP0 functions out of cpu.h | Paolo Bonzini |
2016-05-19 | qemu-common: push cpu.h inclusion out of qemu-common.h | Paolo Bonzini |
2016-05-19 | target-mips: make cpu-qom.h not target specific | Paolo Bonzini |
2016-05-12 | tb: consistently use uint32_t for tb->flags | Emilio G. Cota |
2016-03-30 | target-mips: add MAAR, MAARI register | Yongbok Kim |
2016-03-30 | target-mips: make ITC Configuration Tags accessible to the CPU | Leon Alrae |
2016-03-30 | hw/mips: implement ITC Configuration Tags and Storage Cells | Leon Alrae |
2016-03-30 | hw/mips_malta: add CPS to Malta board | Leon Alrae |
2016-03-30 | target-mips: add CMGCRBase register | Yongbok Kim |
2016-03-23 | target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs | Leon Alrae |
2016-02-26 | target-mips: implement R6 multi-threading | Yongbok Kim |
2016-02-23 | all: Clean up includes | Peter Maydell |
2016-02-19 | target-mips: Stop using uint_fast*_t types in r4k_tlb_t struct | Peter Maydell |
2016-01-23 | target-mips/cpu.h: Fix spell error | Dongxue Zhang |
2015-11-24 | target-mips: flush QEMU TLB when disabling 64-bit addressing | Leon Alrae |
2015-10-30 | target-mips: add PC, XNP reg numbers to RDHWR | Yongbok Kim |
2015-10-29 | target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 | Leon Alrae |
2015-10-29 | target-mips: move the test for enabled interrupts to a separate function | Leon Alrae |
2015-10-07 | target-*: Drop cpu_gen_code define | Richard Henderson |
2015-10-07 | target-mips: Add delayed branch state to insn_start | Richard Henderson |
2015-09-25 | mips: Remove ELF_MACHINE from cpu.h | Peter Crosthwaite |
2015-09-18 | target-mips: improve exception handling | Pavel Dovgaluk |
2015-09-11 | tlb: Add "ifetch" argument to cpu_mmu_index() | Benjamin Herrenschmidt |
2015-08-13 | target-mips: update mips32r5-generic into P5600 | Yongbok Kim |
2015-07-09 | cpu-exec: Purge all uses of ENV_GET_CPU() | Peter Crosthwaite |
2015-06-12 | target-mips: add MTHC0 and MFHC0 instructions | Leon Alrae |
2015-06-12 | target-mips: add CP0.PageGrain.ELPA support | Leon Alrae |
2015-06-12 | target-mips: extend selected CP0 registers to 64-bits in MIPS32 | Leon Alrae |
2015-06-11 | target-mips: add ERETNC instruction and Config5.LLB bit | Leon Alrae |
2015-06-11 | target-mips: add Config5.FRE support allowing Status.FR=0 emulation | Leon Alrae |
2015-03-11 | Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into staging | Peter Maydell |
2015-03-11 | target-mips: add missing MSACSR and restore fp_status and hflags | Leon Alrae |
2015-03-11 | target-mips: replace cpu_save/cpu_load with VMStateDescription | Leon Alrae |
2015-03-10 | cpu: Make cpu_init() return QOM CPUState object | Eduardo Habkost |
2015-01-20 | exec.c: Drop TARGET_HAS_ICE define and checks | Peter Maydell |
2014-12-16 | target-mips: Add missing calls to synchronise SoftFloat status | Maciej W. Rozycki |
2014-12-16 | target-mips: Correct 32-bit address space wrapping | Maciej W. Rozycki |
2014-12-16 | target-mips: Tighten ISA level checks | Maciej W. Rozycki |