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path: root/target-mips/cpu.h
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2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber
Use it for all targets, but be careful not to pass invalid CPUState. cpu_single_env can be NULL, e.g. on Xen. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-20linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung
The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber
Make mips_tcg_init() non-static and add tcg_enabled() check to suppress it for qtest. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson
Clear the DSP hflags at the start of compute_hflags. Otherwise access is not properly disabled once enabled. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori
* afaerber/qom-cpu: (35 commits) target-i386: Pass X86CPU to kvm_handle_halt() target-i386: Pass X86CPU to kvm_get_mp_state() cpu: Move thread_id to CPUState cpus: Pass CPUState to run_on_cpu() target-i386: Pass X86CPU to cpu_x86_inject_mce() target-i386: Pass X86CPU to kvm_mce_inject() cpus: Pass CPUState to [qemu_]cpu_has_work() spapr: Pass PowerPCCPU to hypercalls spapr: Pass PowerPCCPU to spapr_hypercall() target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall target-ppc: Pass PowerPCCPU to powerpc_excp() xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb() cpus: Pass CPUState to qemu_wait_io_event_common() cpus: Pass CPUState to flush_queued_work() cpu: Move queued_work_{first,last} to CPUState cpus: Pass CPUState to qemu_cpu_kick() target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU ppc: Pass PowerPCCPU to {ppc6xx,ppc970,power7,ppc40x,ppce500}_set_irq() cpus: Pass CPUState to qemu_tcg_init_vcpu() cpus: Pass CPUState to qemu_tcg_cpu_thread_fn ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu
Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl
Add an explicit CPUState parameter instead of relying on AREG0 and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki
This change updates the CPU reset sequence to use a common piece of code that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X not being set where applicable that causes floating-point MADD family instructions (and other instructions from the MIPS IV FP subset) to trap. As compute_hflags is now shared between op_helper.c and translate.c, the function is now moved to a common header. There are no changes to this function. The problem was seen with the 24Kf MIPS32r2 processor in user emulation. The new approach prevents system and user emulation from diverging -- all the hflags state is initialized in one place now. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-06-04Kill off cpu_state_reset()Andreas Färber
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber
Turn cpu_init macro into a static inline function returning CPUMIPSState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-05-12target-mips: Remove commented-out function declarationAndreas Färber
There is no function cpu_mips_get_clock(), so drop it. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Stefan Weil <sw@weilnetz.de>
2012-05-01Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl
* 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu: Makefile: Simplify compilation of target-*/cpu.c target-mips: Start QOM'ifying CPU init target-mips: QOM'ify CPU target-m68k: Add QOM CPU subclasses target-m68k: Start QOM'ifying CPU init target-m68k: QOM'ify CPU reset target-m68k: QOM'ify CPU target-sh4: Start QOM'ifying CPU init target-sh4: QOM'ify CPU reset target-sh4: QOM'ify CPU MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes MAINTAINERS: Downgrade target-m68k to Odd Fixes
2012-04-30target-mips: QOM'ify CPUAndreas Färber
Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-28target-mips: Move definition of uint_fast{8, 16}_t to osdep.hAndreas Färber
osdep.h is included via qemu-common.h. Prepares for use of [u]int_fast*_t types in softfloat code. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Ben Taylor <bentaylor.solx86@gmail.com> Cc: Aurélien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Tested-by: Bernhard Walle <bernhard@bwalle.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07Replace Qemu by QEMU in commentsStefan Weil
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2011-12-02fix spelling in target sub directoryDong Xu Wang
Cc: Richard Henderson <rth@twiddle.net> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-09-06mips: Support the MT TCStatus IXMT irq disable flagEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Add MT halting and waking of VPEsEdgar E. Iglesias
+ some partial support for TC's. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30exec.h cleanupBlue Swirl
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20Fix unassigned memory access handlingBlue Swirl
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memory access handling. Fix them by always passing CPUState to the handlers. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-03Fix trivial "endianness bugs"Stefan Weil
Replace endianess -> endianness. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-mips: fix host CPU consumption when guest is idleAurelien Jarno
When the CPU is in wait state, do not wake-up if an interrupt can't be taken. This avoid host CPU running at 100% if a device (e.g. timer) has an interrupt line left enabled. Also factorize code to check if interrupts are enabled in cpu_mips_hw_interrupts_pending(). Based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-06mips: Add support for VInt and VEIC irq modesEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-25mips: more fixes to the MIPS interrupt glue logicAurelien Jarno
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-24mips: Correct MIPS interrupt glue logic for icountEdgar E. Iglesias
When hw interrupt pending bits in CP0_Cause are set, the CPU should see the hw interrupt line as active. The CPU may or may not take the interrupt based on internal state (global irq mask etc) but the glue logic shouldn't care. This fixes MIPS external hw interrupts in combination with -icount. Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-09target-mips: add microMIPS exception handler supportNathan Froyd
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception handlers. The ISA mode is selectable via a user-writable CP0.Config3 flag. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Target specific usermode cleanupPaul Brook
Disable various target specific code that is only relevant to system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-06target-mips: don't call cpu_loop_exit() from helper.cAurelien Jarno
In helper.c AREG0 may not correspond do env, so it's not possible to call cpu_loop_exit() here. Call it from op_helper.c instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add new HFLAGs for JALX and 16/32-bit delay slotsNathan Froyd
We create separate masks for the "basic" branch hflags and the "extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or of those two. This is done to avoid churning the codebase in lots of different places. We also make the execution mode an hflag under MIPS_HFLAG_TMASK Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: add a function to do virtual -> physical translationsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: fix physical address type in MMU functionsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno
Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22target-mips: rename CP0_LLAddr into lladdrAurelien Jarno
The variable CP0_LLAddr represent the full lladdr, not the actual register value, which is only part of this value and depends on the CPU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14mips: fix cpu_reset memory leakBlue Swirl
Remove cpu_mips_register() - move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init() - move the other parts in cpu_mips_init() Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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