| Age | Commit message (Expand) | Author |
|---|
| 2008-07-09 | Use temporary registers for the MIPS FPU emulation. | ths |
| 2008-07-01 | Move interrupt_request and user_mode_only to common cpu state. | pbrook |
| 2008-06-30 | Move CPU save/load registration to common code. | pbrook |
| 2008-06-29 | Add instruction counter. | pbrook |
| 2008-06-27 | More efficient target register / TC accesses. | ths |
| 2008-06-24 | Remove remaining uses of T0 in the MIPS target. | ths |
| 2008-06-24 | T1 is now dead. | ths |
| 2008-06-11 | Move FP TNs to cpu env. | ths |
| 2008-05-30 | Fix typo. | pbrook |
| 2008-05-30 | Move clone() register setup to target specific code. Handle fork-like clone. | pbrook |
| 2008-05-29 | Push common interrupt variables to cpu-defs.h (Glauber Costa) | bellard |
| 2008-05-28 | moved halted field to CPU_COMMON | bellard |
| 2008-05-28 | Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. | ths |
| 2008-05-06 | Use TCG for MIPS GPR moves. | ths |
| 2008-05-04 | Simplify mips branch handling. Retire T2 from use. Use TCG for branches. | ths |
| 2008-02-12 | Make MIPS MT implementation more cache friendly. | ths |
| 2007-12-30 | MIPS COP1X (and related) instructions, by Richard Sandiford. | ths |
| 2007-12-26 | De-cruft exception definitions, and implement nicer debug output. | ths |
| 2007-12-25 | Improved PABITS handling, and config register fixes. | ths |
| 2007-11-10 | added cpu_model parameter to cpu_init() | bellard |
| 2007-11-09 | Move kernel loader parameters from the cpu state to being board specific. | ths |
| 2007-10-28 | Implement missing MIPS supervisor mode bits. | ths |
| 2007-10-20 | Handle IBE on MIPS properly. | ths |
| 2007-10-14 | Replace is_user variable with mmu_idx in softmmu core, | j_mayer |
| 2007-10-12 | Unify '-cpu ?' option. | j_mayer |
| 2007-09-27 | Move get_sp_from_cpustate from cpu.h to target_signal.h. | ths |
| 2007-09-27 | linux-user sigaltstack() syscall, by Thayne Harbaugh. | ths |
| 2007-09-25 | Optimise instructions accessing CP0, by Aurelien Jarno. | ths |
| 2007-09-24 | Per-CPU instruction decoding implementation, by Aurelien Jarno. | ths |
| 2007-09-06 | Partial support for 34K multithreading, not functional yet. | ths |
| 2007-06-23 | Handle MIPS64 SEGBITS value correctly. | ths |
| 2007-06-03 | Move target-specific defines to the target directories. | ths |
| 2007-05-31 | Don't kill the registered irqs on reset. | ths |
| 2007-05-30 | Fix CPU (re-)selection on reset. | ths |
| 2007-05-29 | Fix usermode check, thanks Aurelien Jarno. | ths |
| 2007-05-29 | Don't check the FPU state for each FPU instruction, use hflags to | ths |
| 2007-05-28 | Handle PX/UX status flags correctly, by Aurelien Jarno. | ths |
| 2007-05-23 | The 24k wants more watch and srsmap registers. | ths |
| 2007-05-18 | - Move FPU exception handling into helper functions, since they are big. | ths |
| 2007-05-13 | MIPS linux-user update. | ths |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths |
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths |
| 2007-04-07 | Unify IRQ handling. | pbrook |
| 2007-04-05 | 64bit MIPS FPUs have 32 registers. | ths |
| 2007-03-30 | Fix typo, suggested by Ben Taylor. | ths |
| 2007-03-30 | Sanitize mips exception handling. | ths |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths |
| 2007-03-02 | MIPS Userland TLS register emulation, by Daniel Jacobowitz. | ths |
