Age | Commit message (Collapse) | Author |
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If PVR settings enable illegal insn trap, trap when QEMU finds an
insn it knows nothing about.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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The microblaze gives MMU faults priority. For stores we still
have a flaw that the value leaks to memory in the case of an
unaligned exception.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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* Correct PVR checks for masking off individual exceptions.
* Correct FPU exception code.
* Set EAR on unaligned and unassigned exceptions.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Thanks to Blue Swirl for reporting.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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The microblaze MMU can be synthesized in different configurations.
Have the MMU model show more respect to the chosen configuration.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Untested...
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Raise illegal instruction exceptions when executing instructions that
require units not available on the particulare microblaze configuration.
Also trap priviliege violations made by userspace.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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