Age | Commit message (Expand) | Author |
2015-11-26 | target-i386: kvm: Print warning when clearing mcg_cap bits | Eduardo Habkost |
2015-11-26 | target-i386: kvm: Use env->mcg_cap when setting up MCE | Eduardo Habkost |
2015-11-26 | target-i386: kvm: Abort if MCE bank count is not supported by host | Eduardo Habkost |
2015-11-17 | target-i386: Disable rdtscp on Opteron_G* CPU models | Eduardo Habkost |
2015-11-17 | target-i386: Fix mulx for identical target regs | Richard Henderson |
2015-11-06 | target-i386: Add clflushopt/clwb/pcommit to TCG_7_0_EBX_FEATURES | Xiao Guangrong |
2015-11-06 | target-i386: tcg: Check right CPUID bits for clflushopt/pcommit | Eduardo Habkost |
2015-11-06 | target-i386: tcg: Accept clwb instruction | Eduardo Habkost |
2015-11-05 | target-i386: Enable clflushopt/clwb/pcommit instructions | Xiao Guangrong |
2015-11-05 | target-i386: Remove POPCNT from qemu64 and qemu32 CPU models | Eduardo Habkost |
2015-11-05 | target-i386: Remove ABM from qemu64 CPU model | Eduardo Habkost |
2015-11-05 | target-i386: Remove SSE4a from qemu64 CPU model | Eduardo Habkost |
2015-11-05 | kvmclock: add a new function to update env->tsc. | Liang Li |
2015-11-04 | osdep: Rename qemu_{get, set}_version() to qemu_{, set_}hw_version() | Eduardo Habkost |
2015-11-04 | target-i386: fix pcmpxstrx equal-ordered (strstr) mode | Paolo Bonzini |
2015-10-28 | target-*: Advance pc after recognizing a breakpoint | Richard Henderson |
2015-10-27 | target-i386: Enable "check" mode by default | Eduardo Habkost |
2015-10-27 | target-i386: Don't left shift negative constant | Eduardo Habkost |
2015-10-23 | target-i386: Use 1UL for bit shift | Eduardo Habkost |
2015-10-23 | target-i386: Add DE to TCG_FEATURES | Eduardo Habkost |
2015-10-23 | target-i386: Ensure always-1 bits on DR6 can't be cleared | Eduardo Habkost |
2015-10-23 | target-i386: Check CR4[DE] for processing DR4/DR5 | Richard Henderson |
2015-10-23 | target-i386: Handle I/O breakpoints | Eduardo Habkost |
2015-10-23 | target-i386: Optimize setting dr[0-3] | Richard Henderson |
2015-10-23 | target-i386: Move hw_*breakpoint_* functions | Richard Henderson |
2015-10-23 | target-i386: Ensure bit 10 on DR7 is never cleared | Eduardo Habkost |
2015-10-23 | target-i386: Re-introduce optimal breakpoint removal | Richard Henderson |
2015-10-23 | target-i386: Introduce cpu_x86_update_dr7 | Richard Henderson |
2015-10-23 | target-i386: Disable cache info passthrough by default | Eduardo Habkost |
2015-10-23 | target-i386: allow any alignment for SMBASE | Paolo Bonzini |
2015-10-19 | kvm: Allow the Hyper-V vendor ID to be specified | Alex Williamson |
2015-10-19 | kvm: Move x86-specific functions into target-i386/kvm.c | Thomas Huth |
2015-10-19 | kvm: Pass PCI device pointer to MSI routing functions | Pavel Fedin |
2015-10-12 | target-i386/kvm: Hyper-V HV_X64_MSR_VP_RUNTIME support | Andrey Smetanin |
2015-10-12 | target-i386/kvm: set Hyper-V features cpuid bit HV_X64_MSR_VP_INDEX_AVAILABLE | Andrey Smetanin |
2015-10-12 | target-i386/kvm: Hyper-V HV_X64_MSR_RESET support | Andrey Smetanin |
2015-10-09 | qdev: Protect device-list-properties against broken devices | Markus Armbruster |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson |
2015-10-07 | tcg: Pass data argument to restore_state_to_opc | Richard Henderson |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson |
2015-10-07 | target-*: Drop cpu_gen_code define | Richard Henderson |
2015-10-07 | target-i386: Add cc_op state to insn_start | Richard Henderson |
2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson |
2015-10-02 | cpu/apic: drop icc bus/bridge | Chen Fan |
2015-10-02 | apic: move APIC's MMIO region mapping into APIC | Chen Fan |
2015-10-02 | Correctly re-init EFER state during INIT IPI | Bill Paul |
2015-10-02 | target-i386: add ABM to Haswell* and Broadwell* CPU models | Paolo Bonzini |