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2016-02-13target-i386: Rearrange processing of 0F AERichard Henderson
Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Also, add some missing #UD checks for e.g. incorrect LOCK prefix. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Rearrange processing of 0F 01Richard Henderson
Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Fixes incorrect decoding of AMD Pacifica extensions (aka vmrun et al) via op==2 path. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Split fxsave/fxrstor implementationRichard Henderson
We will be able to reuse these pieces for XSAVE/XRSTOR. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-09target-i386: fix PSE36 modePaolo Bonzini
(pde & 0x1fe000) is a 32-bit integer; when shifting it into bits 39-32 the result is zero. Fix it by making the mask (and thus the result of the AND) a 64-bit integer. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Deconstruct the cpu_T arrayRichard Henderson
All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1436426122-12276-11-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Tidy gen_add_A0_imRichard Henderson
Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-10-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite leaveRichard Henderson
Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite gen_enter inlineRichard Henderson
Use gen_lea_v_seg for centralized segment base knowledge. Unify code across 32- and 64-bit. Fix note about "must save state" before using the out-of-line helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-8-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson
More centralization of handling of segment bases. Also fixes the note about 16-bit wrap around not fully handled. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-7-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Access segs via TCG registersRichard Henderson
Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-6-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson
I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson
Centralize handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-4-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Introduce mo_stacksizeRichard Henderson
Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Create gen_lea_v_segRichard Henderson
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case; use this new function to implement gen_string_movl_A0_EDI, gen_string_movl_A0_ESI, gen_add_A0_ds_seg. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-2-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2016-02-09' into ↵Peter Maydell
staging QAPI patches for 2016-02-09 # gpg: Signature made Tue 09 Feb 2016 10:55:51 GMT using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-qapi-2016-02-09: (31 commits) qapi: Add missing JSON files in build dependencies qapi: Fix compilation failure on MIPS and SPARC qmp: Don't abuse stack to track qmp-output root qmp: Fix reference-counting of qnull on empty output visit qapi: Drop unused error argument for list and implicit struct qapi: Tighten qmp_input_end_list() qapi: Drop unused 'kind' for struct/enum visit qapi: Swap 'name' in visit_* callbacks to match public API qom: Swap 'name' next to visitor in ObjectPropertyAccessor qapi: Swap visit_* arguments for consistent 'name' placement qom: Use typedef for Visitor qapi: Don't cast Enum* to int* qapi: Consolidate visitor small integer callbacks qapi: Make all visitors supply uint64 callbacks qapi: Prefer type_int64 over type_int in visitors qapi-visit: Kill unused visit_end_union() qapi: Track all failures between visit_start/stop qapi: Improve generated event use of qapi visitor balloon: Improve use of qapi visitor vl: Ensure qapi visitor properly ends struct visit ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-09tcg: Remove lingering references to gen_opc_bufRichard Henderson
Three in comments and one in code in the stub tcg_liveness_analysis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-08qom: Swap 'name' next to visitor in ObjectPropertyAccessorEric Blake
Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-02-08qapi: Swap visit_* arguments for consistent 'name' placementEric Blake
JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-02-08qom: Use typedef for VisitorEric Blake
No need to repeat 'struct Visitor' when we already have it in typedefs.h. Omitting the redundant 'struct' also makes a later patch easier to search for all object property callbacks that are associated with a Visitor. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1454075341-13658-18-git-send-email-eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-01-29x86: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-11-git-send-email-peter.maydell@linaro.org
2016-01-21Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging X86 queue, 2016-01-21 # gpg: Signature made Thu 21 Jan 2016 15:08:40 GMT using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" * remotes/ehabkost/tags/x86-pull-request: target-i386: Add PKU and and OSPKE support target-i386: Add support to migrate vcpu's TSC rate target-i386: Reorganize TSC rate setting code target-i386: Fallback vcpu's TSC rate to value returned by KVM target-i386: Add suffixes to MMReg struct fields target-i386: Define MMREG_UNION macro target-i386: Define MMXReg._d field target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* target-i386: Rename struct XMMReg to ZMMReg target-i386: Use a _q array on MMXReg too target-i386/ops_sse.h: Use MMX_Q macro target-i386: Rename optimize_flags_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-i386: Add PKU and and OSPKE supportHuaitong Han
Add PKU and OSPKE CPUID features, including xsave state and migration support. Signed-off-by: Huaitong Han <huaitong.han@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: squashed 3 patches together, edited patch description] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add support to migrate vcpu's TSC rateHaozhong Zhang
This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration will not be aborted and QEMU on the destination will not set vcpu's TSC rate to the migrated value. If vcpu's TSC rate specified by CPU option 'tsc-freq' on the destination machine is inconsistent with the migrated TSC rate, the migration will be aborted. For backwards compatibility, the migration of vcpu's TSC rate is disabled on pc-*-2.5 and older machine types. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Rewrote comment at kvm_arch_put_registers()] [ehabkost: Moved compat code to pc-2.5] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Reorganize TSC rate setting codeHaozhong Zhang
Following changes are made to the TSC rate setting code in kvm_arch_init_vcpu(): * The code is moved to a new function kvm_arch_set_tsc_khz(). * If kvm_arch_set_tsc_khz() fails, i.e. following two conditions are both satisfied: * KVM does not support the TSC scaling or it fails to set vcpu's TSC rate by KVM_SET_TSC_KHZ, * the TSC rate to be set is different than the value currently used by KVM, then kvm_arch_init_vcpu() will fail. Prevously, * the lack of TSC scaling never failed kvm_arch_init_vcpu(), * the failure of KVM_SET_TSC_KHZ failed kvm_arch_init_vcpu() unconditionally, even though the TSC rate to be set is identical to the value currently used by KVM. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Fallback vcpu's TSC rate to value returned by KVMHaozhong Zhang
If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. This patch does not change the current functionality of QEMU and just prepares for later patches to enable migrating vcpu's TSC rate. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Add suffixes to MMReg struct fieldsEduardo Habkost
This will ensure we never use the MMX_* and ZMM_* macros with the wrong struct type. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMREG_UNION macroEduardo Habkost
This will simplify the definitions of ZMMReg and MMXReg. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Define MMXReg._d fieldEduardo Habkost
Add a new field and reorder MMXReg fields, to make MMXReg and ZMMReg field lists look the same (except for the array sizes). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost
They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost
The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Use a _q array on MMXReg tooEduardo Habkost
Make MMXReg use the same field names used on XMMReg, so we can try to reuse macros and other code later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386/ops_sse.h: Use MMX_Q macroEduardo Habkost
We have a MMX_Q macro in addition to MMX_{B,W,L}. Use it. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename optimize_flags_init()Eduardo Habkost
Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21exec.c: Allow target CPUs to define multiple AddressSpacesPeter Maydell
Allow multiple calls to cpu_address_space_init(); each call adds an entry to the cpu->ases array at the specified index. It is up to the target-specific CPU code to actually use these extra address spaces. Since this multiple AddressSpace support won't work with KVM, add an assertion to avoid confusing failures. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21exec.c: Don't set cpu->as until cpu_address_space_initPeter Maydell
Rather than setting cpu->as unconditionally in cpu_exec_init (and then having target-i386 override this later), don't set it until the first call to cpu_address_space_init. This requires us to initialise the address space for both TCG and KVM (KVM doesn't need the AS listener but it does require cpu->as to be set). For target CPUs which don't set up any address spaces (currently everything except i386), add the default address_space_memory in qemu_init_vcpu(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-15target-i386: do not duplicate page protection checksPaolo Bonzini
x86_cpu_handle_mmu_fault is currently checking twice for writability and executability of pages; the first time to decide whether to trigger a page fault, the second time to compute the "prot" argument to tlb_set_page_with_attrs. Reorganize code so that first "prot" is computed, then it is used to check whether to raise a page fault, then finally PROT_WRITE is removed if the D bit will have to be set. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386: kvm: clear unusable segments' flags in migrationMichael Chapman
This commit fixes migration of a QEMU/KVM guest from kernel >= v3.9 to kernel <= v3.7 (e.g. from RHEL 7 to RHEL 6). Without this commit a guest migrated across these kernel versions fails to resume on the target host as its segment descriptors are invalid. Two separate kernel commits combined together to result in this bug: commit f0495f9b9992f80f82b14306946444b287193390 Author: Avi Kivity <avi@redhat.com> Date: Thu Jun 7 17:06:10 2012 +0300 KVM: VMX: Relax check on unusable segment Some userspace (e.g. QEMU 1.1) munge the d and g bits of segment descriptors, causing us not to recognize them as unusable segments with emulate_invalid_guest_state=1. Relax the check by testing for segment not present (a non-present segment cannot be usable). Signed-off-by: Avi Kivity <avi@redhat.com> commit 25391454e73e3156202264eb3c473825afe4bc94 Author: Gleb Natapov <gleb@redhat.com> Date: Mon Jan 21 15:36:46 2013 +0200 KVM: VMX: don't clobber segment AR of unusable segments. Usability is returned in unusable field, so not need to clobber entire AR. Callers have to know how to deal with unusable segments already since if emulate_invalid_guest_state=true AR is not zeroed. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> The first commit changed the KVM_SET_SREGS ioctl so that it did no treat segment flags == 0 as an unusable segment, instead only looking at the "present" flag. The second commit changed KVM_GET_SREGS so that it did not clear the flags of an unusable segment. Since QEMU does not itself maintain the "unusable" flag across a migration, the end result is that unusable segments read from a kernel with these commits and loaded into a kernel without these commits are not properly recognised as being unusable. This commit updates both get_seg and set_seg so that the problem is avoided even when migrating to or migrating from a QEMU without this commit. In get_seg, we clear the segment flags if the segment is marked unusable. In set_seg, we mark the segment unusable if the segment's "present" flag is not set. Signed-off-by: Michael Chapman <mike@very.puzzling.org> Message-Id: <1449464047-17467-1-git-send-email-mike@very.puzzling.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17kvm: x86: add support for KVM_CAP_SPLIT_IRQCHIPPaolo Bonzini
This patch adds support for split IRQ chip mode. When KVM_CAP_SPLIT_IRQCHIP is enabled: 1.) The PIC, PIT, and IOAPIC are implemented in userspace while the LAPIC is implemented by KVM. 2.) The software IOAPIC delivers interrupts to the KVM LAPIC via kvm_set_irq. Interrupt delivery is configured via the MSI routing table, for which routes are reserved in target-i386/kvm.c then configured in hw/intc/ioapic.c 3.) KVM delivers IOAPIC EOIs via a new exit KVM_EXIT_IOAPIC_EOI, which is handled in target-i386/kvm.c and relayed to the software IOAPIC via ioapic_eoi_broadcast. Signed-off-by: Matt Gingell <gingell@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/kvm: Hyper-V SynIC timers MSR's supportAndrey Smetanin
Hyper-V SynIC timers are host timers that are configurable by guest through corresponding MSR's (HV_X64_MSR_STIMER*). Guest setup and use fired by host events(SynIC interrupt and appropriate timer expiration message) as guest clock events. The state of Hyper-V SynIC timers are stored in corresponding MSR's. This patch seria implements such MSR's support and migration. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Denis V. Lunev <den@openvz.org> CC: Roman Kagan <rkagan@virtuozzo.com> CC: kvm@vger.kernel.org Message-Id: <1448464885-8300-3-git-send-email-asmetanin@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/hyperv: Hyper-V SynIC SINT routing and vcpu exitAndrey Smetanin
Hyper-V SynIC(synthetic interrupt controller) helpers for Hyper-V SynIC irq routing setup, irq injection, irq ack notifications event/message pages changes tracking for future use. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17target-i386/kvm: Hyper-V SynIC MSR's supportAndrey Smetanin
This patch does Hyper-V Synthetic interrupt controller(Hyper-V SynIC) MSR's support and migration. Hyper-V SynIC is enabled by cpu's 'hv-synic' option. This patch does not allow cpu creation if 'hv-synic' option specified but kernel doesn't support Hyper-V SynIC. Changes v3: * removed 'msr_hv_synic_version' migration because it's value always the same * moved SynIC msr's initialization into kvm_arch_init_vcpu Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-11-26target-i386: kvm: Print warning when clearing mcg_cap bitsEduardo Habkost
Instead of silently clearing mcg_cap bits when the host doesn't support them, print a warning when doing that. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [Avoid \n at end of error_report. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1448471956-66873-10-git-send-email-pbonzini@redhat.com>
2015-11-26target-i386: kvm: Use env->mcg_cap when setting up MCEEduardo Habkost
When setting up MCE, instead of using the MCE_*_DEF macros directly, just filter the existing env->mcg_cap value. As env->mcg_cap is already initialized as MCE_CAP_DEF|MCE_BANKS_DEF at target-i386/cpu.c:mce_init(), this doesn't change any behavior. But it will allow us to change mce_init() in the future, to implement different defaults depending on CPU model, machine-type or command-line parameters. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1448471956-66873-9-git-send-email-pbonzini@redhat.com>
2015-11-26target-i386: kvm: Abort if MCE bank count is not supported by hostEduardo Habkost
Instead of silently changing the number of banks in mcg_cap based on kvm_get_mce_cap_supported(), abort initialization if the host doesn't support MCE_BANKS_DEF banks. Note that MCE_BANKS_DEF was always 10 since it was introduced in QEMU, and Linux always returned 32 at KVM_CAP_MCE since KVM_CAP_MCE was introduced, so no behavior is being changed and the error can't be triggered by any Linux version. The point of the new check is to ensure we won't silently change the bank count if we change MCE_BANKS_DEF or make the bank count configurable in the future. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [Avoid Yoda condition and \n at end of error_report. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1448471956-66873-8-git-send-email-pbonzini@redhat.com>
2015-11-17target-i386: Disable rdtscp on Opteron_G* CPU modelsEduardo Habkost
KVM can't virtualize rdtscp on AMD CPUs yet, so there's no point in enabling it by default on AMD CPU models, as all we are getting are confused users because of the "host doesn't support requested feature" warnings. Disable rdtscp on Opteron_G* models, but keep compatibility on pc-*-2.4 and older (just in case there are people are doing funny stuff using AMD CPU models on Intel hosts). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-17target-i386: Fix mulx for identical target regsRichard Henderson
The Intel specification clearly indicates that the low part of the result is written first and the high part of the result is written second; thus if ModRM:reg and VEX.vvvv are identical, the final result should be the high part of the result. At present, TCG may either produce incorrect results or crash with --enable-checking. Reported-by: Toni Nedialkov <farmdve@gmail.com> Reported-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-06target-i386: Add clflushopt/clwb/pcommit to TCG_7_0_EBX_FEATURESXiao Guangrong
Now these instructions are handled by TCG and can be added to the TCG_7_0_EBX_FEATURES macro. Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-06target-i386: tcg: Check right CPUID bits for clflushopt/pcommitEduardo Habkost
Detect the clflushopt and pcommit instructions and check their corresponding feature flags, instead of checking CPUID_SSE and CPUID_CLFLUSH. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-02 17:50:11 +0000