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2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-05target-*: dfilter support for in_asmRichard Henderson
The arm target was handled by 06486077, but other targets were ignored. This handles all the rest which actually support disassembly (that is, skipping moxie and tilegx). Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-05-23target-i386: Move TCG initialization check to tcg_x86_init()Eduardo Habkost
Instead of requiring cpu.c to check if TCG was already initialized, simply let the function be called multiple times. Suggested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-05-23target-i386: key sfence availability on CPUID_SSE, not CPUID_SSE2Paolo Bonzini
sfence was introduced before lfence and mfence. This fixes Linux 2.4's measurement of checksumming speeds for the pIII_sse algorithm: md: linear personality registered as nr 1 md: raid0 personality registered as nr 2 md: raid1 personality registered as nr 3 md: raid5 personality registered as nr 4 raid5: measuring checksumming speed 8regs : 384.400 MB/sec 32regs : 259.200 MB/sec invalid operand: 0000 CPU: 0 EIP: 0010:[<c0240b2a>] Not tainted EFLAGS: 00000246 eax: c15d8000 ebx: 00000000 ecx: 00000000 edx: c15d5000 esi: 8005003b edi: 00000004 ebp: 00000000 esp: c15bdf50 ds: 0018 es: 0018 ss: 0018 Process swapper (pid: 1, stackpage=c15bd000) Stack: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000206 c0241c6c 00001000 c15d4000 c15d7000 c15d4000 c15d4000 Call Trace: [<c0241c6c>] [<c0105000>] [<c0241db4>] [<c010503b>] [<c0105000>] [<c0107416>] [<c0105030>] Code: 0f ae f8 0f 10 04 24 0f 10 4c 24 10 0f 10 54 24 20 0f 10 5c <0>Kernel panic: Attempted to kill init! Reported-by: Stefan Weil <sw@weilnetz.de> Fixes: 121f3157887f92268a3d6169e2d4601f9292020b Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
In user mode, there's only a static address translation, TBs are always invalidated properly and direct jumps are reset when mapping change. Thus the destination address is always valid for direct jumps and there's no need to restrict it to the pages the TB resides in. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-05-12tcg: Clean up direct block chaining safety checksSergey Fedorov
We don't take care of direct jumps when address mapping changes. Thus we must be sure to generate direct jumps so that they always keep valid even if address mapping changes. Luckily, we can only allow to execute a TB if it was generated from the pages which match with current mapping. Document tcg_gen_goto_tb() declaration and note the reason for destination PC limitations. Some targets with variable length instructions allow TB to straddle a page boundary. However, we make sure that both of TB pages match the current address mapping when looking up TBs. So it is safe to do direct jumps into the both pages. Correct the checks for some of those targets. Given that, we can safely patch a TB which spans two pages. Remove the unnecessary check in cpu_exec() and allow such TBs to be patched. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota
We are inconsistent with the type of tb->flags: usage varies loosely between int and uint64_t. Settle to uint32_t everywhere, which is superior to both: at least one target (aarch64) uses the most significant bit in the u32, and uint64_t is wasteful. Compile-tested for all targets. Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1460049562-23517-1-git-send-email-cota@braap.org>
2016-03-24target-i386: implement PKE for TCGPaolo Bonzini
Tested with kvm-unit-tests. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14target-i386: Dump unknown opcodes with -d unimpRichard Henderson
We discriminate here between opcodes that are illegal in the current cpu mode or with illegal arguments (such as modrm.mod == 3) and encodings that are unknown (such as an unimplemented isa extension). Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Fix inhibit irq mask handlingRichard Henderson
The patch in 7f0b714 was too simplistic, in that we wound up setting the flag and then resetting it immediately in gen_eob. Fixes the reported boot problem with Windows XP. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Use gen_nop_modrm for prefetch instructionsRichard Henderson
Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Fix addr16 prefixPaolo Bonzini
While ADDSEG will only be false in 16-bit mode for LEA, it can be false even in other cases when 16-bit addresses are obtained via the 67h prefix in 32-bit mode. In this case, gen_lea_v_seg forgets to add a nonzero FS or GS base if CS/DS/ES/SS are all zero. This case is pretty rare but happens when booting Windows 95/98, and this patch fixes it. The bug is visible since commit d6a291498, but it was introduced together with gen_lea_v_seg and it probably could be reproduced with a "addr16 gs movsb" instruction as early as in commit ca2f29f555805d07fb0b9ebfbbfc4e3656530977. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456931078-21635-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Fix SMSW for 64-bit modeRichard Henderson
In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Fix SMSW and LMSW from/to registerPaolo Bonzini
SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386: Rearrange processing of 0F 01", 2016-02-13) did not account for that. Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-14target-i386: Avoid repeated calls to the bnd_jmp helperPaolo Bonzini
Two flags were tested the wrong way. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845145-18891-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> [rth: Fixed enable test as well.]
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-02-15target-i386: Implement FSGSBASERichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-15target-i386: Clear bndregs during legacy near jumpsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-15target-i386: Implement BNDLDX, BNDSTXRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-15target-i386: Implement BNDCL, BNDCU, BNDCNRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-15target-i386: Implement BNDMOVRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-15target-i386: Implement BNDMKRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Split up gen_lea_modrmRichard Henderson
This is immediately usable by lea and multi-byte nop, and will be required to implement parts of the mpx spec. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Perform set/reset_inhibit_irq inlineRichard Henderson
With helpers that can be reused for other things. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Enable control registers for MPXRichard Henderson
Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Implement XSAVEOPTRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Add XSAVE extensionRichard Henderson
This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Rearrange processing of 0F AERichard Henderson
Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Also, add some missing #UD checks for e.g. incorrect LOCK prefix. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Rearrange processing of 0F 01Richard Henderson
Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Fixes incorrect decoding of AMD Pacifica extensions (aka vmrun et al) via op==2 path. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-13target-i386: Split fxsave/fxrstor implementationRichard Henderson
We will be able to reuse these pieces for XSAVE/XRSTOR. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-09target-i386: Deconstruct the cpu_T arrayRichard Henderson
All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1436426122-12276-11-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Tidy gen_add_A0_imRichard Henderson
Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-10-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite leaveRichard Henderson
Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite gen_enter inlineRichard Henderson
Use gen_lea_v_seg for centralized segment base knowledge. Unify code across 32- and 64-bit. Fix note about "must save state" before using the out-of-line helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-8-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson
More centralization of handling of segment bases. Also fixes the note about 16-bit wrap around not fully handled. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-7-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Access segs via TCG registersRichard Henderson
Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-6-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson
I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson
Centralize handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-4-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Introduce mo_stacksizeRichard Henderson
Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Create gen_lea_v_segRichard Henderson
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case; use this new function to implement gen_string_movl_A0_EDI, gen_string_movl_A0_ESI, gen_add_A0_ds_seg. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-2-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-09tcg: Remove lingering references to gen_opc_bufRichard Henderson
Three in comments and one in code in the stub tcg_liveness_analysis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-01-29x86: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-11-git-send-email-peter.maydell@linaro.org
2016-01-21target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost
They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost
The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-01-21target-i386: Rename optimize_flags_init()Eduardo Habkost
Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-17target-i386: Fix mulx for identical target regsRichard Henderson
The Intel specification clearly indicates that the low part of the result is written first and the high part of the result is written second; thus if ModRM:reg and VEX.vvvv are identical, the final result should be the high part of the result. At present, TCG may either produce incorrect results or crash with --enable-checking. Reported-by: Toni Nedialkov <farmdve@gmail.com> Reported-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-11-06target-i386: tcg: Check right CPUID bits for clflushopt/pcommitEduardo Habkost
Detect the clflushopt and pcommit instructions and check their corresponding feature flags, instead of checking CPUID_SSE and CPUID_CLFLUSH. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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