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path: root/target-i386/ops_sse.h
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2014-06-16target-i386: Use Common ShiftRows and InvShiftRows TablesTom Musta
This patch eliminates the (now) redundant copy of the Advanced Encryption Standard (AES) ShiftRows and InvShiftRows tables; the code is updated to use the common tables declared in include/qemu/aes.h. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-13target-i386: add AES-NI instructionsAurelien Jarno
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-13target-i386: add pclmulqdq instructionAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheelAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarityAurelien Jarno
valids can equals to -1 if the reg/mem string is empty. Change the expression to have an empty xor mask in that case. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" modeAurelien Jarno
The inner loop should only change the current bit of the result, instead of the whole result. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" modeAurelien Jarno
pcmpXstrX instructions in "Equal each" mode force both invalid element pair to true. It means (upper - MAX(valids, validd)) bits should be set to 1, not (upper - MAX(valids, validd) + 1). Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" modeAurelien Jarno
Fix the order of the of the comparisons to match the "Intel 64 and IA-32 Architectures Software Developer's Manual". Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstrm instructionsAurelien Jarno
pcmpXstrm instructions returns their result in the XMM0 register and not in the first operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpXstri instructionsAurelien Jarno
ffs1 returns the first bit set to one starting counting from the most significant bit. pcmpXstri returns the most significant bit set to one, starting counting from the least significant bit. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.2: fix pcmpgtq instructionAurelien Jarno
The "Intel 64 and IA-32 Architectures Software Developer's Manual" (at least recent versions) clearly says that the comparison is signed. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-14x86: avoid AREG0 for FPU helpersBlue Swirl
Make FPU helpers take a parameter for CPUState instead of relying on global env. Introduce temporary wrappers for FPU load and store ops. Remove wrappers for non-AREG0 code. Don't call unconverted helpers directly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-28x86: fix coding style in ops_sse.hBlue Swirl
Fix coding style in ops_sse.h before next commit. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-01-11target-i386: fix dpps and dppd SSE2 instructionsAurelien Jarno
The helpers implemented dpps and dppd SSE instructions are not passing the correct argument types to the softfloat functions. While they do work anyway providing a correct behaviour, this patch fixes that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11target-i386: fix round{pd,ps,sd,ss} SSE2 instructionsAurelien Jarno
roundps and roundss SSE2 instructions have been broken when switching target-i386 to softfloat. They use float64_round_to_int to convert a float32, and while the implicit conversion from float32 to float64 was correct for softfloat-native, it is not for pure softfloat. Fix that by using the correct registers and correct functions. Also fix roundpd and roundsd implementation at the same time, even if these functions are behaving correctly. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11target-i386: fix {min,max}{pd,ps,sd,ss} SSE2 instructionsAurelien Jarno
minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2 instructions have been broken when switching target-i386 to softfloat. It's not possible to use comparison instructions on float types anymore to softfloat, so use the floatXX_lt function instead, as the float_XX_min and float_XX_max functions can't be used due to the Intel specific behaviour. As it implements the correct NaNs behaviour, let's remove the corresponding entry from the TODO. It fixes GDM screen display on Debian Lenny. Thanks to Peter Maydell and Jason Wessel for their analysis of the problem. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-11-19x86: fix pcmpestrm and pcmpistrmBlue Swirl
Fix obvious typos (decrement and off-by-one error) in pcmpestrm and pcmpistrm which resulted in infinite loop. Reported by Frank Mehnert, spotted also by Coverity (bug 84752853). Reported-by: Frank Mehnert <frank.mehnert@oracle.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17target-i386: Fix several SSE3 instructions.Max Reitz
haddp[sd], hsubp[sd] and addsubp[sd] operate on floats, thus it is necessary to use the appropriate floating point calculation functions. If this is not done, those functions operate merely on integers, which is not correct. Signed-off-by: Max Reitz <max@tyndur.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-25target-i386: replace approx_rsqrt and approx_rcp by softfloat opsAurelien Jarno
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17softfloat: rename float*_eq() into float*_eq_quiet()Aurelien Jarno
float*_eq functions have a different semantics than other comparison functions. Fix that by first renaming float*_quiet() into float*_eq_quiet(). Note that it is purely mechanical, and the behaviour should be unchanged. That said it clearly highlight problems due to this different semantics, they are fixed later in this patch series. Cc: Alexander Graf <agraf@suse.de> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-i386: fix CMPUNORDPS/D and CMPORDPS/D instructionsAurelien Jarno
SSE instructions CMPUNORDPS/D and CMPORDPS/D do not trigger an invalid exception if operands are qNANs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04target-i386: add SSE4a instruction supportAndre Przywara
This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-05Fix Sparse warnings: add "static"Blue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13Replace gcc variadic macro extension with C99 versionBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Remove FORCE_RET() and RETURN()aurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01Fix pmovsx* / pmovzx* SSE instructions (original fix by Frank Mehnert).balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5841 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-16target-i386: fix helper_pmovmskb_mmx helperaurel32
(malc) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5728 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04Fix crc32w decoding, fix a constant width in blendvpd.balrog
Forced the constant's width to long long so that it doesn't overflow, problem spotted by C. W. Betts. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5417 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04Implement SSE4.1, SSE4.2 (x86).balrog
This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT extensions. Most instructions haven't been tested yet. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25Implement x86 SSSE3 instructions.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-15converted more helpers to TCG - fixed some SVM issuesbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12converted SSE/MMX ops to TCGbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-083DNow! instruction set emulationaurel32
(Michael Tross) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4180 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in ↵ths
the regex. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-16fixed movd mmx/sse insnbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2321 c046a42c-6fe2-441c-8c8c-71466251a162
2005-04-26removed switches in op.c (Paul Brook)bellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1400 c046a42c-6fe2-441c-8c8c-71466251a162
2005-03-20NaN support in FPU comparisonsbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1341 c046a42c-6fe2-441c-8c8c-71466251a162
2005-03-13soft float supportbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1336 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-23FORCE_RET() fixes - fpu fixesbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1236 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-16sse fixbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1224 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-08MMX/SSE supportbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1205 c046a42c-6fe2-441c-8c8c-71466251a162
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