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path: root/target-i386/op_helper.c
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2010-10-13i386: avoid a write only variableBlue Swirl
Compiling with GCC 4.6.0 20100925 produced warnings: /src/qemu/target-i386/op_helper.c: In function 'switch_tss': /src/qemu/target-i386/op_helper.c:283:53: error: variable 'new_trap' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Add also pointer to docs. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-22target-i386: svm: Fix MSRPM checkAdam Lackorzynski
Correct the calculation of the offset in the msrpm for the MSR range 0 - 0x1fff. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-07-03remove unused stuff from */exec.hPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-30x86: svm: Always clear event_inj on vmexitJan Kiszka
We currently only clear SVM_EVTINJ_VALID after successful interrupt delivery. This apparently does not match real hardware which clears the whole event_inj field on every vmexit, including unsuccessful interrupt delivery. Reported-by: Erik van der Kouwe <vdkouwe@cs.vu.nl> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-19apic: avoid passing CPUState from CPU codeBlue Swirl
Pass only APICState when accessing APIC from CPU code. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-08target-i386: Fix variable in (disabled) debugging codeAdam Lackorzynski
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-01Move ioport.h out of cpu-all.hPaul Brook
Only include ioport.h where it is actually needed. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-28target-i386: fix crash on x86 32bit linux host with hw breakpoint exceptionsJason Wessel
If you make use of hw breakpoints on a 32bit x86 linux host, qemu will segmentation fault when processing the exception. The problem is that the value of env is stored in $ebp in the op_helper raise_exception() function, and it can have the wrong value when calling it from non generated code. It is possible to work around the problem by restoring the value of env before calling raise_exception() using a new helper function that takes (CPUState *) as one of the arguments. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-i386: implement lzcnt emulationAndre Przywara
lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04target-i386: Fix exceptions for fxsave/fxrstorKevin Wolf
This patch corrects the following aspects of exception generation in fxsave/fxrstor: * Generate #GP if the operand is not aligned to a 16 byte boundary * Generate #UD if the LOCK prefix is used * For CR0.EM = 1 #NM is generated, not #UD Signed-off-by: Kevin Wolf <mail@kevin-wolf.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04target-i386: add RDTSCP supportAndre Przywara
RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-20ioports: remove unused env parameter and compile only onceBlue Swirl
The CPU state parameter is not used, remove it and adjust callers. Now we can compile ioport.c once for all targets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-24Unbreak large mem support by removing kqemuAnthony Liguori
kqemu introduces a number of restrictions on the i386 target. The worst is that it prevents large memory from working in the default build. Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on the TSC as a time source which will not be reliable on a multiple processor system in userspace. Since most modern processors are multicore, this severely limits the utility of kqemu. kvm is a viable alternative for people looking to accelerate qemu and has the benefit of being supported by the upstream Linux kernel. If someone can implement work arounds to remove the restrictions introduced by kqemu, I'm happy to avoid and/or revert this patch. N.B. kqemu will still function in the 0.11 series but this patch removes it from the 0.12 series. Paul, please Ack or Nack this patch. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-09QEMU: MCE: Add MCE simulation to qemu/tcgHuang Ying
- MCE features are initialized when VCPU is intialized according to CPUID. - A monitor command "mce" is added to inject a MCE. - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE. aliguori: fix build for linux-user Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22x86: Add support for resume flagJan Kiszka
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2009-04-23Fix i386-linux-user build (Laurent Desnogues)aliguori
This broke due to r7230. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7233 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-22put valid data into exit_int_info if needed (Gleb Natapov)aliguori
If fault happened during event delivery exit_int_info should contain valid info about the event on vm exit. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7230 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-19kqemu: merge CONFIG_KQEMU and USE_KQEMUblueswir1
Basically a recursive ":%s/USE_KQEMU/CONFIG_KQEMU/g". Signed-off-by: Paul Bolle <pebolle@tiscali.nl> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7189 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-20x86: Add NULL check to lsl (Jan Kiszka)aliguori
According to the Intel specs, lsl performs a check against NULL for the provided selector, just like lar does. helper_lar() includes the corresponding code, helper_lsl() was lacking it so far. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6863 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-27x86: use qemu_log_mask on triple faults (Chris Wright)aliguori
replace open coded qemu_log_mask with proper macro Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6649 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09KVM: CPUID takes ecx as input value for some functions (Amit Shah)aliguori
The CPUID instruction takes the value of ECX as an input parameter in addition to the value of EAX as the count for functions 4, 0xb and 0xd. Make sure we pass the value to the instruction. Also convert to the qemu-style whitespace for the surrounding code. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6565 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-02Implement FFXSR (Alexander Graf)aliguori
Newer AMD CPUs have the FFXSR capability. This leaves out XMM register in FXSAVE/FXRESTORE when in CPL=0 and 64-bit mode. This is required for Hyper-V. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6500 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-01Replace noreturn with QEMU_NORETURNmalc
Thanks to Robert Riebisch for analysis [1] [1] http://marc.info/?l=qemu-devel&m=123352293319271&w=2 git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6492 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29Use new logging API in reset handling (Jan Kiszka)aliguori
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6473 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29MTRR support on x86, part 2 (Carl-Daniel Hailfinger)aliguori
Load and save MTRR state together with machine state. Add support for the MTRRcap MSR which is used by the latest Bochs BIOS and some operating systems. Fix a typo in ext2_feature_name. With this patch, MTRR emulation should be good enough to not trigger any sanity checks in well behaved BIOS/kernel code. Some corner cases for BIOS/firmware usage remain to be implemented, but that can be deferred to another patch. Also, MTRR accesses on hardware not supporting MTRRs should cause #GP. That can be enforced by another patch as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6472 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26x86: Issue reset on triple faults (Jan Kiszka)aliguori
As discussed a few times on this list: A triple fault causes a system reset on x86, and some guests make use of this (e.g. 386BSD). To keep the chance of tracing unexpected resets, log them if CPU_LOG_RESET is set. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6453 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26MTRR support on x86 (Carl-Daniel Hailfinger)aliguori
The current codebase ignores MTRR (Memory Type Range Register) configuration writes and reads because Qemu does not implement caching. All BIOS/firmware in know of for x86 do implement a mode called Cache-as-RAM (CAR) which locks down the CPU cache lines and uses the CPU cache like RAM before RAM is enabled. Qemu assumes RAM is accessible from the start, but it would be nice to be able to run real BIOS/firmware in Qemu. For that, we need CAR support and for CAR support we have to support MTRRs. This patch is a first step in that direction. MTRRs are MSRs supported by all recent x86 CPUs, even old i586. Besides influencing cache, the MTRRs can be written and read back, so discarding MTRR writes violates the expectations of existing code out there. An added benefit of this patch is that it fixes the following Linux kernel error message present in recent kernels (provided the BIOS has the recent MTRR patches applied): ------------[ cut here ]------------ WARNING: at arch/x86/kernel/cpu/mtrr/main.c:1500 mtrr_trim_uncached_memory+0x382/0x384() WARNING: strange, CPU MTRRs all blank? Modules linked in: Supported: Yes Pid: 0, comm: swapper Not tainted 2.6.27.7-9-default #1 [<c0106570>] dump_trace+0x6b/0x249 [<c01070a5>] show_trace+0x20/0x39 [<c0343c02>] dump_stack+0x71/0x76 [<c012acb2>] warn_slowpath+0x6f/0x90 [<c0542f8f>] mtrr_trim_uncached_memory+0x382/0x384 [<c053f24d>] setup_arch+0x40d/0x639 [<c053a6ac>] start_kernel+0x6b/0x31f ======================= ---[ end trace 4eaa2a86a8e2da22 ]--- Handle common x86 MTRR reads and writes, but don't act on them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6449 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori
These are references to 'loglevel' that aren't on a simple 'if (loglevel & X) qemu_log()' statement. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori
This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15Clean up debugging code #ifdefs (Eduardo Habkost)aliguori
Use macros to avoid #ifdefs on debugging code. This patch doesn't try to merge logging macros from different files, but just unify the debugging code #ifdefs onto a macro on each file. A further cleanup can unify the debugging macros on a common header, later Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14Suppress i386 warningsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6304 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14Add noreturn function attributeblueswir1
Introduce noreturn attribute and attach it to cpu_loop_exit as well as interrupt/exception helpers for i386. This avoids a bunch of gcc4 warnings. [ Note that this patch comes with a workaround to include qemu-common.h even in cases where is currently causes conflicts with dyngen-exec.h. I've been told that these conflicts will get resolved in the future (/me will try to have a look as well - as time permits). ] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6303 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13x86 cleanupblueswir1
Remove some unnecessary includes, add needed includes, move prototypes to cpu.h to suppress missing prototype warnings. Remove unused functions and prototypes (cpu_x86_flush_tlb, cpu_lock, cpu_unlock, restore_native_fp_state, save_native_fp_state). Make some functions and data static (f15rk, parity_table, rclw_table, rclb_table, raise_interrupt, fpu_raise_exception), they are not used outside op_helper.c anymore. Make some x86_64 and user only code conditional to avoid warnings. Document where each function is implemented in cpu.h and exec.h. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6005 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07Remove FORCE_RET() and RETURN()aurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18x86: Debug register emulation (Jan Kiszka)aliguori
Built on top of previously enhanced breakpoint/watchpoint support, this patch adds full debug register emulation for the x86 architecture. Many corner cases were considered, and the result was successfully tested inside a Linux guest with gdb, but I won't be surprised if one or two scenarios still behave differently in reality. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5747 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-05Split CPUID from op_helperaliguori
KVM needs to call CPUID from outside of the TCG code. This patch splits out the CPUID logic into a separate helper that both the op helper and KVM can call. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5626 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-26Fix undeclared symbol warnings from sparseblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-17i386/SVM: return amount of ASIDsaurel32
With SVM the TLB supports tagging to distinguish TLB entries from different virtual CPUs. This tag is called an ASID. The amount of ASIDs is given in EBX of the SVM-CPUID-leaf. Currently we return 0, which might break hypervisors. Let's better return something >0 here, say 0x10. Since we're flushing the complete TLB on every VM entry and exit we're not making use of the ASID information anyways. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5496 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-14target-i386: Add Core Duo Definitionaurel32
This patch adds a CPU definition for the Core Duo CPU. I tried to resemble the original as closely as possible and document what features are missing still. This patch enables the use of a recent CPU definition on 32 bit platforms. It also fixes two issues that went along the line: - invalid xlevel in core2duo spec While looking though the CPUIDs again, I found that xlevel is actually 8. - non-PSE36 support The CoreDuo CPUID does not expose the PSE36 capability, but CPUID 0x80000008 is tied to 36 bits. This broke Windows XP installation for me, so I just set it to 32 bits width when PSE36 is not available. The original CPU also exposes 32 bit width in CPUID 0x80000008. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5488 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-02Do not use load_seg_vm to load CS in real mode iret handlingmalc
load_seg_vm calls cpu_x86_load_seg_cache which updates hflags of current env, real hardware doesn't do this, nor the code that handles real mode lret/lcall/ljmp. This unbreaks "unreal mode" and makes QEMU the first emulator being able to run Project Angel demo by IMPACT Studios. (Not that there are many physical machines out there capable of doing the same) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5403 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-30Handle MSR_IA32_PERF_STATUS in rdmsr (Alexander Graf).balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5366 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29My core2duo patch introduced a vague statement of "missing features" in pbrook
the CPUID specification. This patch addresses this by specifying exactly what is missing. While going along the missing CPUID entries I also stumbled across invalid and missing CPUID #defines while comparing them to the Intel Documentation. This patch also addresses these. I found them too minor to split them up in a separate patch. Furthermore I looked through CPUID functions > 5 and realized that it should be safe to bump the level to 10. I tried booting Linux with that and it worked fine. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5350 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).balrog
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25Core 2 Duo specification (Alexander Graf).balrog
This patch adds a Core 2 Duo CPU to the available CPU types. The CPU definition tries to resemble a real CPU as good as possible, whilst not exposing features qemu does not implement. The patch also includes some minor additions that Core 2 Duo CPUs have: - New MSR: MSR_IA32_PERF_STATUS - CPUID up to level 5 (cache info and mwait) Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5317 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Fix up pxe boot (Glauber Costa)aliguori
As discussed in http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html, current pxe boot is broken for some use cases. The problem goes away if we reduce the number of allowed bits in the address space to 32 (which has the side effect of reducing guest max mem size to 4Gb). After digging for a while, it turns out that it happens because pxelinux tries to access address 0x10009e9a6, which does not fit a 32-bit address. A closer look, however, reveals this access is totally valid: It's just 0x9e9a6 with an add carry. To avoid this, this patch casts the address passed to the POPL macro to a 32-bit value. This is also done, although just theorectically, for PUSHL too. Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Reported-by: Chris Lalancette <clalance@redhat.com> CC: Eduardo Habkost <ehabkost@redhat.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5182 c046a42c-6fe2-441c-8c8c-71466251a162
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