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path: root/target-i386/machine.c
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2009-10-04target-i386: add RDTSCP supportAndre Przywara
RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-27kvm: Simplify cpu_synchronize_state()Avi Kivity
cpu_synchronize_state() is a little unreadable since the 'modified' argument isn't self-explanatory. Simplify it by making it always synchronize the kernel state into qemu, and automatically flush the registers back to the kernel if they've been synchronized on this exit. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-09QEMU: MCE: Add MCE simulation to qemu/tcgHuang Ying
- MCE features are initialized when VCPU is intialized according to CPUID. - A monitor command "mce" is added to inject a MCE. - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE. aliguori: fix build for linux-user Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-02Use ctz64 in favor of ffsllJan Kiszka
Not all host platforms support ffsll. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2009-06-29KVM: x86: Refactor persistent CPU stateJan Kiszka
This patch aligns the KVM-related layout and encoding of the CPU state to be saved to disk or migrated with qemu-kvm. The major differences are reordering of fields and a compressed interrupt_bitmap into a single number as there can be no more than one pending IRQ at a time. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22kvm: x86: Save/restore KVM-specific CPU statesJan Kiszka
Save and restore all so far neglected KVM-specific CPU states. Handling the TSC stabilizes migration in KVM mode. The interrupt_bitmap and mp_state are currently unused, but will become relevant for in-kernel irqchip support. By including proper saving/restoring already, we avoid having to increment CPU_SAVE_VERSION later on once again. v2: - initialize mp_state runnable (for the boot CPU) Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-22kvm: Add missing bits to support live migrationJan Kiszka
This patch adds the missing hooks to allow live migration in KVM mode. It adds proper synchronization before/after saving/restoring the VCPU states (note: PPC is untested), hooks into cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging at KVM level, and synchronizes that drity log into QEMU's view before running ram_live_save(). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21Convert machine registration to use module init functionsAnthony Liguori
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-04-22xen: groundwork for xen support (Gerd Hoffmann)aliguori
- configure script and build system changes. - wind up new machine type. - add -xen-* command line options. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7219 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-29MTRR support on x86, part 2 (Carl-Daniel Hailfinger)aliguori
Load and save MTRR state together with machine state. Add support for the MTRRcap MSR which is used by the latest Bochs BIOS and some operating systems. Fix a typo in ext2_feature_name. With this patch, MTRR emulation should be good enough to not trigger any sanity checks in well behaved BIOS/kernel code. Some corner cases for BIOS/firmware usage remain to be implemented, but that can be deferred to another patch. Also, MTRR accesses on hardware not supporting MTRRs should cause #GP. That can be enforced by another patch as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6472 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18x86: Debug register emulation (Jan Kiszka)aliguori
Built on top of previously enhanced breakpoint/watchpoint support, this patch adds full debug register emulation for the x86 architecture. Many corner cases were considered, and the result was successfully tested inside a Linux guest with gdb, but I won't be surprised if one or two scenarios still behave differently in reality. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5747 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-29Fix restore of older snapshots for target-i386 on big endian hostsaliguori
A target_ulong may be 64-bit. Passing it to a function expecting a 32-bit pointer is wrong and unfortunately happens to work for x86. It won't work on big endian hosts though. Change the code to work properly on all hosts. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-02Resurrect the safe part of r5274blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5401 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29Fix save/restore regression introduced by r5318aliguori
sysenter_cs is a u32 and is loaded as a u32. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5351 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25Revert r5274 which breaks savevm/loadvmblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5321 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).balrog
On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20Add signed versions of save/load functionsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook
Save and restore env->interrupt_request and env->halted. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-04save more CPU statebellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4669 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04Correctly save and restore env->a20_mask now that it is a 64-bitaurel32
variable. Noticed by Erik de Castro Lopo. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4334 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04remove target ifdefs from vl.caurel32
(Glauber Costa) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
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