Age | Commit message (Expand) | Author |
---|---|---|
2004-02-07 | fixed WP semantics | bellard |
2004-02-03 | more precise TLB invalidation - init cleanup | bellard |
2004-01-24 | combine PDE and PTE protections as in intel specs - added cpu_get_phys_page_d... | bellard |
2004-01-18 | fixed dirty bit support for 4M pages (L4 Pistachio fix) | bellard |
2004-01-13 | fixed subtle bug: in some cases PG_DIRTY was not set correctly | bellard |
2004-01-04 | correct value for ADDSEG is real mode (fixes GRUB boot) - update static prote... | bellard |
2004-01-04 | debug fixes - use more generic TLB mappings | bellard |
2003-12-02 | dump irq inhibit flag as it is a part of the cpu state | bellard |
2003-11-23 | a20 fix | bellard |
2003-11-19 | always completely redefine the TLB in case of MMU fault | bellard |
2003-11-12 | dump more registers | bellard |
2003-11-04 | a20 support | bellard |
2003-10-27 | full softmmu support | bellard |
2003-09-30 | new directory structure | bellard |