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2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-05cpu_dump_state: move DUMP_FPU and DUMP_CCOP flags from x86-only to genericPeter Maydell
Move the DUMP_FPU and DUMP_CCOP flags for cpu_dump_state() from being x86-specific flags to being generic ones. This allows us to drop some TARGET_I386 ifdefs in various places, and means that we can (potentially) be more consistent across architectures about which monitor commands or debug abort printouts include FPU register contents and info about QEMU's condition-code optimisations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-01x86: Implement SMEP and SMAPH. Peter Anvin
This patch implements Supervisor Mode Execution Prevention (SMEP) and Supervisor Mode Access Prevention (SMAP) for x86. The purpose of the patch, obviously, is to help kernel developers debug the support for those features. A fair bit of the code relates to the handling of CPUID features. The CPUID code probably would get greatly simplified if all the feature bit words were unified into a single vector object, but in the interest of producing a minimal patch for SMEP/SMAP, and because I had very limited time for this project, I followed the existing style. [ v2: don't change the definition of the qemu64 CPU shorthand, since that breaks loading old snapshots. Per Anthony Liguori this can be fixed once the CPU feature set is snapshot. Change the coding style slightly to conform to checkpatch.pl. ] Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-09Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemuBlue Swirl
* 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu: target-i386: move tcg initialization into x86_cpu_initfn() cleanup cpu_set_debug_excp_handler target-xtensa: drop usage of prev_debug_excp_handler target-i386: drop usage of prev_debug_excp_handler
2012-08-01target-i386: move cpu halted decision into x86_cpu_resetIgor Mammedov
MP initialization protocol differs between cpu families, and for P6 and onward models it is up to CPU to decide if it will be BSP using this protocol, so try to model this. However there is no point in implementing MP initialization protocol in qemu. Thus first CPU is always marked as BSP. This patch: - moves decision to designate BSP from board into cpu, making cpu self-sufficient in this regard. Later it will allow to cleanup hw/pc.c and remove cpu_reset and wrappers from there. - stores flag that CPU is BSP in IA32_APIC_BASE to model behavior described in Inted SDM vol 3a part 1 chapter 8.4.1 - uses MSR_IA32_APICBASE_BSP flag in apic_base for checking if cpu is BSP patch is based on Jan Kiszka's proposal: http://thread.gmane.org/gmane.comp.emulators.qemu/100806 Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-28x86: avoid AREG0 for exceptionsBlue Swirl
Add an explicit CPUX86State parameter instead of relying on AREG0. Merge raise_exception_env() to raise_exception(), likewise with raise_exception_err_env() and raise_exception_err(). Introduce cpu_svm_check_intercept_param() and cpu_vmexit() as wrappers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-25target-i386: move tcg initialization into x86_cpu_initfn()Igor Mammedov
In order to make cpu object not depended on external ad-hoc initialization routines, move tcg initialization from cpu_x86_init inside cpu object "x86_cpu_initfn()". Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-25target-i386: drop usage of prev_debug_excp_handlerIgor Mammedov
Chains of exception handlers are currently unused feature, drop it for now so as not to expose prev_debug_excp_handler at global scope when moving tcg initialization into target-i386/cpu.c Later we probably could re-invent better interface for this. Signed-off-by: Igor Mammedov <imammedo@redhat.com>
2012-06-04Kill off cpu_state_reset()Andreas Färber
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-i386: Let cpu_x86_init() return X86CPUAndreas Färber
Turn cpu_init macro into a static inline function returning CPUX86State for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-06-04target-i386: Pass X86CPU to do_cpu_{init,sipi}()Andreas Färber
Allows to use cpu_reset() in place of cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-05-12target-i386: Defer MCE initAndreas Färber
Commit de024815e3b523addf58f1f79846b7fe74643678 (target-i386: QOM'ify CPU init) moved mce_init() call from helper.c:cpu_x86_init() into X86CPU's cpu.c:x86_cpu_initfn(). mce_init() checks for a family >= 6 though, so we could end up with a sequence such as for -cpu somecpu,family=6: x86_cpu_initfn => X86CPU::family == 5 mce_init => no-op cpu_x86_register => X86CPU::family = 6 => MCE unexpectedly not init'ed or for -cpu someothercpu,family=5: x86_cpu_initfn => X86CPU::family == 6 mce_init => init'ed cpu_x86_register => X86CPU::family = 5 => MCE unexpectedly init'ed Therefore partially revert the above commit. To avoid moving mce_init() back into helper.c, foresightedly move it into a new x86_cpu_realize() function and, in lack of ObjectClass::realize, call it directly from cpu_x86_init(). While at it, move the qemu_init_vcpu() call that used to follow mce_init() in cpu_x86_init() into the new realizefn as well. Reported-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Pass X86CPU to cpu_x86_register()Andreas Färber
Avoids an x86_env_get_cpu() call there, to work with QOM properties. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-10target-i386: QOM'ify CPU resetAndreas Färber
Move code from cpu_state_reset() into QOM x86_cpu_reset(), fixing style issues for FPU init. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-10target-i386: QOM'ify CPU initAndreas Färber
Move code from cpu_x86_init() to new QOM x86_cpu_initfn(). Also move mce_init() to cpu.c since it's used nowhere else. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-10target-i386: QOM'ify CPUAndreas Färber
Embed CPUX86State as first member of X86CPU. Distinguish between "x86_64-cpu" and "i386-cpu". Drop cpu_x86_close() in favor of calling object_delete() directly. For now let CPUClass::reset() call cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-03-14target-i386: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-11target-i386: Mask NX bit from cpu_get_phys_page_debug resultJan Kiszka
This was a long pending bug, now revealed by the assert in phys_page_find that stumbled over the large page index returned by cpu_get_phys_page_debug for NX-marked pages: We need to mask out NX and all user-definable bits 52..62 from PDEs and the final PTE to avoid corrupting physical addresses. Reviewed-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl
* 'upstream' of git://qemu.weilnetz.de/qemu: Move definition of HOST_LONG_BITS to qemu-common.h target-xtensa: Clean includes target-unicore32: Clean includes target-sh4: Clean includes target-s390x: Clean includes target-ppc: Clean includes target-mips: Clean includes target-microblaze: Clean includes target-m68k: Clean includes target-lm32: Clean includes target-i386: Clean includes target-cris: Clean includes target-arm: Clean includes target-alpha: Clean includes Remove macro HOST_LONG_SIZE
2012-02-28target-i386: Clean includesStefan Weil
Remove some include statements which are not needed. Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-18target-i386: Add infrastructure for reporting TPR MMIO accessesJan Kiszka
This will allow the APIC core to file a TPR access report. Depending on the accelerator and kernel irqchip mode, it will either be delivered right away or queued for later reporting. In TCG mode, we can restart the triggering instruction and can therefore forward the event directly. KVM does not allows us to restart, so we postpone the delivery of events recording in the user space APIC until the current instruction is completed. Note that KVM without in-kernel irqchip will report the address after the instruction that triggered the access. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-02Fix X86 CPU topology in KVM modeBharata B Rao
apic id returned to guest kernel in ebx for cpuid(function=1) depends on CPUX86State->cpuid_apic_id which gets populated after the cpuid information is cached in the host kernel. This results in broken CPU topology in guest. Fix this by setting cpuid_apic_id before cpuid information is passed to the host kernel. This is done by moving the setting of cpuid_apic_id to cpu_x86_init() where it will work for both KVM as well as TCG modes. Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Bharata B Rao <bharata.rao@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-10-24i386: wire up MSR_IA32_MISC_ENABLEAvi Kivity
It's needed for its default value - bit 0 specifies that "rep movs" is good enough for memcpy, and Linux may use a slower memcpu if it is not set, depending on cpu family/model. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-05Avoid allocating TCG resources in non-TCG modeJan Kiszka
Do not allocate TCG-only resources like the translation buffer when running over KVM or XEN. Saves a "few" bytes in the qemu address space and is also conceptually cleaner. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-30exec.h cleanupBlue Swirl
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-08Fix compilation warning due to missing header for sigaction (followup)Alexandre Raymond
This patch removes all references to signal.h when qemu-common.h is included as they become redundant. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-06-03target-i386: remove old code handling float64Aurelien Jarno
Now that target-i386 uses softfloat, floatx80 is always available and there is no need anymore to have code handling both float64 and floax80. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17target-i386: use CPU_LDoubleU instead of a private unionAurelien Jarno
Use CPU_LDoubleU in cpu_dump_state() instead of redefining a union for doing the conversion. Based on a patch from Laurent Vivier <laurent@vivier.eu>. Cc: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-16x86: Properly reset PAT MSRJan Kiszka
Conforming to the Intel spec, set the power-on value of PAT also on reset, but save it across INIT. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15kvm: x86: Consolidate TCG and KVM MCE injection codeJan Kiszka
This switches KVM's MCE injection path to cpu_x86_inject_mce, both for SIGBUS and monitor initiated events. This means we prepare the MCA MSRs in the VCPUState also for KVM. We have to drop the MSRs writeback restrictions for this purpose which is now safe as every uncoordinated MSR injection is removed with this patch. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15x86: Run qemu_inject_x86_mce on target VCPUJan Kiszka
We will use the current TCG-only MCE injection path for KVM as well, and then this read-modify-write of the target VCPU state has to be performed synchronously in the corresponding thread. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15x86: Optionally avoid injecting AO MCEs while others are pendingJan Kiszka
Allow to tell cpu_x86_inject_mce that it should ignore Action Optional MCE events when the target VCPU is still processing another one. This will be used by KVM soon. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15x86: Refine error reporting of MCE injection servicesJan Kiszka
As this service is used by the human monitor, make sure that errors get reported to the right channel, and also raise the verbosity. This requires to move Monitor typedef in qemu-common.h to resolve the include dependency. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15x86: Small cleanups of MCE helpersJan Kiszka
Fix some code style issues, use proper headers, and align to cpu_x86 naming scheme. No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-03-15x86: Perform implicit mcg_status resetJan Kiszka
Reorder mcg_status in CPUState to achieve automatic clearing on reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> CC: Huang Ying <ying.huang@intel.com> CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> CC: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-02-08x86: Fix MCA broadcast parameters for TCG caseJan Kiszka
When broadcasting MCEs, we need to set MCIP and RIPV in mcg_status like it is done for KVM. Use the symbolic constants at this chance. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-23x86: Optionally dump code bytes on cpu_dump_stateJan Kiszka
Introduce the cpu_dump_state flag CPU_DUMP_CODE and implement it for x86. This writes out the code bytes around the current instruction pointer. Make use of this feature in KVM to help debugging fatal vm exits. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-01-21Add function for checking mca broadcast of CPUJin Dongming
Add function for checking whether current CPU support mca broadcast. Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-01-21Add "broadcast" option for mce commandJin Dongming
When the following test case is injected with mce command, maybe user could not get the expected result. DATA command cpu bank status mcg_status addr misc (qemu) mce 1 1 0xbd00000000000000 0x05 0x1234 0x8c Expected Result panic type: "Fatal Machine check" That is because each mce command can only inject the given cpu and could not inject mce interrupt to other cpus. So user will get the following result: panic type: "Fatal machine check on current CPU" "broadcast" option is used for injecting dummy data into other cpus. Injecting mce with this option the expected result could be gotten. Usage: Broadcast[on] command broadcast cpu bank status mcg_status addr misc (qemu) mce -b 1 1 0xbd00000000000000 0x05 0x1234 0x8c Broadcast[off] command cpu bank status mcg_status addr misc (qemu) mce 1 1 0xbd00000000000000 0x05 0x1234 0x8c Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-01-21Clean up cpu_inject_x86_mce()Jin Dongming
Clean up cpu_inject_x86_mce() for later patch. Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-12-27x86: Filter out garbage from segment flags dumpJan Kiszka
Only bits 8..23 of the segment flags contain valid data, so only dump those when printing the CPU state. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-20MCE: Relay UCR MCE to guestMarcelo Tosatti
Port qemu-kvm's commit 4b62fff1101a7ad77553147717a8bd3bf79df7ef Author: Huang Ying <ying.huang@intel.com> Date: Mon Sep 21 10:43:25 2009 +0800 MCE: Relay UCR MCE to guest UCR (uncorrected recovery) MCE is supported in recent Intel CPUs, where some hardware error such as some memory error can be reported without PCC (processor context corrupted). To recover from such MCE, the corresponding memory will be unmapped, and all processes accessing the memory will be killed via SIGBUS. For KVM, if QEMU/KVM is killed, all guest processes will be killed too. So we relay SIGBUS from host OS to guest system via a UCR MCE injection. Then guest OS can isolate corresponding memory and kill necessary guest processes only. SIGBUS sent to main thread (not VCPU threads) will be broadcast to all VCPU threads as UCR MCE. aliguori: fix build Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-10-20kvm: x86: add mce supportMarcelo Tosatti
Port qemu-kvm's MCE support commit c68b2374c9048812f488e00ffb95db66c0bc07a7 Author: Huang Ying <ying.huang@intel.com> Date: Mon Jul 20 10:00:53 2009 +0800 Add MCE simulation support to qemu/kvm KVM ioctls are used to initialize MCE simulation and inject MCE. The real MCE simulation is implemented in Linux kernel. The Kernel part has been merged. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2010-06-27x86: Fix INIT processingJan Kiszka
This fixes a regression of 0e26b7b892: Reset halted also on INIT. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19apic: avoid passing CPUState from CPU codeBlue Swirl
Pass only APICState when accessing APIC from CPU code. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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