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AgeCommit message (Expand)Author
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell
2014-08-19arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall
2014-08-19target-arm: Implement MDSCR_EL1 as having statePeter Maydell
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell
2014-08-19target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell
2014-08-19target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell
2014-08-19target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell
2014-08-19target-arm: Collect up the debug cp register definitionsPeter Maydell
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova
2014-08-04target-arm: A64: fix TLB flush instructionsAlex Bennée
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias
2014-08-04target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias
2014-08-04target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias
2014-07-08target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell
2014-06-24Fix new typos (found by codespell)Stefan Weil
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar
2014-06-19target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar
2014-06-19target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possiblePranavkumar Sawargaonkar
2014-06-19target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar
2014-06-19target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell
2014-06-19target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell
2014-06-19target-arm: Add ULL suffix to calculation of page sizePeter Maydell
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler
2014-06-16target-arm: Use Common Tables in AES InstructionsTom Musta
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell
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