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AgeCommit message (Expand)Author
2014-12-11target-arm: Check error conditions on kvm_arm_reset_vcpuChristoffer Dall
2014-12-11target-arm: Support save/load for 64 bit CPUsPeter Maydell
2014-12-11target-arm/kvm: make reg sync code common between kvm32/64Alex Bennée
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler
2014-12-11target-arm: make VBAR bankedGreg Bellows
2014-12-11target-arm: make PAR bankedFabian Aggeler
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler
2014-12-11target-arm: make DFSR bankedFabian Aggeler
2014-12-11target-arm: make IFSR bankedFabian Aggeler
2014-12-11target-arm: make DACR bankedFabian Aggeler
2014-12-11target-arm: make TTBCR bankedFabian Aggeler
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler
2014-12-11target-arm: make CSSELR bankedFabian Aggeler
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler
2014-12-11target-arm: add MVBAR supportFabian Aggeler
2014-12-11target-arm: add SDER definitionGreg Bellows
2014-12-11target-arm: add NSACR registerFabian Aggeler
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov
2014-12-11target-arm: add banked register accessorsFabian Aggeler
2014-12-11target-arm: add async excp target_el functionGreg Bellows
2014-12-11target-arm: extend async excp maskingGreg Bellows
2014-12-11Pass semihosting exit code back to system.Liviu Ionescu
2014-11-17target-arm: handle address translations that start at level 3Peter Maydell
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell
2014-11-04target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell
2014-11-04target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell
2014-11-04target-arm/translate.c: Don't use IS_M()Peter Maydell
2014-11-04target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell
2014-11-04target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell
2014-11-02target-arm: A64: remove redundant storeAlex Bennée
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell
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